01666nlm0 22004571i 450 9900092369504033219783540744429000923695FED01000923695(Aleph)000923695FED0100092369520100926d2007----km-y0itay50------baengDEdrnn-008mamaaIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and SimulationRisorsa elettronica17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007. Proceedingsedited by Nadine Azémard, LaBerlin ; HeidelbergSpringer2007Lecture Notes in Computer Science0302-97434644Documento elettronicoTestoFormato html, pdfAzémard,NadineSvensson,LarsITUNINAREICATUNIMARCFull text per gli utenti Federico IIhttp://dx.doi.org/10.1007/978-3-540-74442-9EB990009236950403321Arithmetic and Logic StructuresCircuits and SystemsComputer scienceComputer ScienceComputer system performanceLogic designLogic DesignMemory management (Computer science)Memory StructuresProcessor ArchitecturesSystem Performance and EvaluationSystems engineeringIntegrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation772134UNINA