01920nam1 2200373 i 450 PUV039600220231121125614.0888587635819990424d1998 ||||0itac50 baitaitz01i xxxe z01n˜La œriforma della Chiesa per la restaurazione cristiana della societàle visite apostoliche delle diocesi e dei seminari d'Italia promosse durante il pontificato di Pio 10. (1903-1914)Giovanni VianRomaHerder editrice e libreria19982 v.25 cm.001PUV03960032000 1Giovanni Vian1001PUV03960042000 2Giovanni Vian2Pio<papa ; 10.>RiformeFIRRMLC423369IVisite pastoraliItalia1903-1914FIRRMLC423370IChiesa cattolica romanaItalia1903-1914FIRRMLC118564I282.4521Vian, Giovanni <1963- >AUFV001418070306779ITIT-0119990424IT-RM0281 IT-FR0084 IT-RM0151 IT-FR0017 BIBLIOTECA VALLICELLIANARM0281 Biblioteca Del Monumento Nazionale Di MontecassinoFR0084 Biblioteca Istituto Storico Italiano Medio Evo - IRM0151 Biblioteca umanistica Giorgio ApreaFR0017 PUV0396002Biblioteca umanistica Giorgio Aprea 52CIS 8/448.1 52VM 0000862095 VM barcode:00081321. - Inventario:38656 FLSVMA 2011012720121204 52CIS 8/448.2 52VM 0000862085 VM barcode:8/448.200081320. - Inventario:38659 FLSVMA 2011012720121204 08 25 41 52Riforma della Chiesa per la restaurazione cristiana della società920781UNICAS07810nam 2200625 a 450 991048456430332120200520144314.03-540-36863-910.1007/11802839(CKB)1000000000233058(SSID)ssj0000319780(PQKBManifestationID)11937751(PQKBTitleCode)TC0000319780(PQKBWorkID)10338748(PQKB)10021946(DE-He213)978-3-540-36863-2(MiAaPQ)EBC3068262(PPN)12313689X(EXLCZ)99100000000023305820060623d2006 uy 0engurnn|008mamaatxtccrReconfigurable computing architectures and applications : second international workshop, ARC 2006, Delft, The Netherlands, March 1-3, 2006 : revised selected papers /Koen Bertels, Joao M.P. Cardoso, Stamatis Vassiliadis (eds.)1st ed. 2006.Berlin Springer20061 online resource (XVI, 469 p.) Lecture notes in computer science,0302-9743 ;3985LNCS sublibrary. SL 1, Theoretical computer science and general issuesBibliographic Level Mode of Issuance: Monograph3-540-36708-X Includes bibliographical references and index.Applications -- Implementation of Realtime and Highspeed Phase Detector on FPGA -- Case Study: Implementation of a Virtual Instrument on a Dynamically Reconfigurable Platform -- Configurable Embedded Core for Controlling Electro-Mechanical Systems -- Evaluation of a Locomotion Algorithm for Worm-Like Robots on FPGA-Embedded Processors -- Dynamic Partial Reconfigurable FIR Filter Design -- Event-Driven Simulation Engine for Spiking Neural Networks on a Chip -- Towards an Optimal Implementation of MLP in FPGA -- Power -- Energy Consumption for Transport of Control Information on a Segmented Software-Controlled Communication Architecture -- Quality Driven Dynamic Low Power Reconfiguration of Handhelds -- An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects -- Image Processing -- Highly Paralellized Architecture for Image Motion Estimation -- Design Exploration of a Video Pre-processor for an FPGA Based SoC -- QUKU: A Fast Run Time Reconfigurable Platform for Image Edge Detection -- Applications of Small-Scale Reconfigurability to Graphics Processors -- An Embedded Multi-camera System for Simultaneous Localization and Mapping -- Performance/Cost Trade-Off Evaluation for the DCT Implementation on the Dynamically Reconfigurable Processor -- Trigonometric Computing Embedded in a Dynamically Reconfigurable CORDIC System-on-Chip -- Handel-C Design Enhancement for FPGA-Based DV Decoder -- Run-Time Resources Management on Coarse Grained, Packet-Switching Reconfigurable Architecture: A Case Study Through the APACHES’ Platform -- A New VLSI Architecture of Lifting-Based DWT -- Architecture Based on FPGA’s for Real-Time Image Processing -- Real Time Image Processing on a Portable Aid Device for Low Vision Patients -- General Purpose Real-Time Image Segmentation System -- Organization and Architecture -- Implementation of LPM Address Generators on FPGAs -- Self Reconfiguring EPIC Soft Core Processors -- Constant Complexity Management of 2D HW Multitasking in Run-Time Reconfigurable FPGAs -- Area/Performance Improvement of NoC Architectures -- Implementation of Inner Product Architecture for Increased Flexibility in Bitwidths of Input Array -- A Flexible Multi-port Caching Scheme for Reconfigurable Platforms -- Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support -- A Reconfigurable Data Cache for Adaptive Processors -- The Emergence of Non-von Neumann Processors -- Scheduling Reconfiguration Activities of Run-Time Reconfigurable RTOS Using an Aperiodic Task Server -- A New Approach to Assess Defragmentation Strategies in Dynamically Reconfigurable FPGAs -- A 1,632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI -- PISC: Polymorphic Instruction Set Computers -- Networks and Communication -- Generic Network Interfaces for Plug and Play NoC Based Architecture -- Providing QoS Guarantees in a NoC by Virtual Channel Reservation -- Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA -- A Reconfigurable Architecture for MIMO Square Root Decoder -- Security -- Time-Memory Trade-Off Attack on FPGA Platforms: UNIX Password Cracking -- Updates on the Security of FPGAs Against Power Analysis Attacks -- Reconfigurable Modular Arithmetic Logic Unit for High-Performance Public-Key Cryptosystems -- FPGA Implementation of a GF(2 m ) Tate Pairing Architecture -- Iterative Modular Division over GF(2 m ): Novel Algorithm and Implementations on FPGA -- Mobile Fingerprint Identification Using a Hardware Accelerated Biometric Service Provider -- UNITE: Uniform Hardware-Based Network Intrusion deTection Engine -- Tools -- Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs -- Automatic Compilation Framework for Bloom Filter Based Intrusion Detection -- A Basic Data Routing Model for a Coarse-Grain Reconfigurable Hardware -- Hardware and a Tool Chain for ADRES -- Integrating Custom Instruction Specifications into C Development Processes -- A Compiler-Oriented Architecture Description for Reconfigurable Systems -- Dynamic Instruction Merging and a Reconfigurable Array: Dataflow Execution with Software Compatibility -- High-Level Synthesis Using SPARK and Systolic Array -- Super Semi-systolic Array-Based Application-Specific PLD Architecture.1 The International Workshop on Recon?gurable Computing (ARC) started in 2005 in Algarve, Portugal. The major motivation was to create an event where on-going research e?orts as well as more elaborated, interesting and hi- quality work on applied recon?gurable computing could be presented and d- cussed. Over the last couple of years recon?gurable computing has become a we- known and established research area producing interesting as well as important results in both general and embedded computing systems. It is also getting more and more interest from industry which is attracted by the (design and development) ?exibility as well as the performance improvements that can be expected from this technology. As recon?gurablecomputing has blurred the gap between software and hardware, some even speak of a radical new programming paradigm opening a new realm of unseen applications and opportunities. The logo of the ARC workshop is the Nonius, a measurement instrument used in the Portuguese period of discoveries that was invented by Pedro Nunes, a Portuguesemathematician. As the logo suggests,the main motto of ARC is to help to navigate the world of recon?gurable computing. Driven by this motto, we hope ARC contributes to solid advances on recon?gurable computing.Lecture notes in computer science ;3985.LNCS sublibrary.SL 1,Theoretical computer science and general issues.ARC 2006Adaptive computing systemsCongressesField programmable gate arraysCongressesAdaptive computing systemsField programmable gate arrays003.3Bertels Koen1236863Cardoso Joao M. P1752221Vassiliadis Stamatis882255ARC (Symposium)MiAaPQMiAaPQMiAaPQBOOK9910484564303321Reconfigurable computing4189680UNINA02764oam 2200541I 450 991015033790332120240808105431.01-138-91571-81-315-69008-X1-317-42604-510.4324/9781315690087(CKB)3710000000932843(MiAaPQ)EBC4741984(OCoLC)970390252(EXLCZ)99371000000093284320180706d2017 uy 0engurcnu||||||||rdacontentrdamediardacarrierThe Marshall Plan a new deal for Europe /Michael HolmFirst edition.New York :Routledge,2017.1 online resource (192 pages) illustrations, photographs, tablesCritical moments in American history1-138-91570-X 1-317-42605-3 Includes bibliographical references and index.Acknowledgements -- Time line -- A new deal for the world : American plans for the Post-World War II order -- The world America made : towards the Marshall Plan, 1945-1947 -- Creating the European recovery program, 1947-1948 -- The Marshall plan in action and the emergence of European unity, 1948-1951 -- Epilogue: the Marshall Plan and memory -- Documents -- Bibliography.Between 1948 and 1951, the Marshall Plan delivered an unprecedented $12.3 billion in U.S. aid to help Western European countries recover from the destruction of the Second World War, and forestall Communist influence in that region. The Marshall Plan: A New Deal for Europe examines the aid program, its ideological origins and explores how ideas about an Americanized world order inspired and influenced the Marshall Plan’s creation and execution. The book provides a much-needed re-examination of the Plan, enabling students to understand its immediate impact and its political, social, and cultural legacy. Including essential primary documents, this concise book will be a key resource for students of America’s role in the world at mid-century.Critical moments in American history.Reconstruction (1939-1951)Economic assistance, AmericanEuropeForeign economic relationsUnited StatesUnited StatesForeign economic relationsEuropeReconstruction (1939-1951)Economic assistance, American.338.91/7304338.917304Holm Michael1975-892619MiAaPQMiAaPQMiAaPQBOOK9910150337903321The Marshall Plan1993863UNINA