01088nam0 22002773i 450 VAN024617920220524123043.73N978-981-33-4642-020220520d2021 |0itac50 baengSG|||| |||||ASIC Design and SynthesisRTL Design Using VerilogVaibbhav TaraateSingaporeSpringer2021XXI, 330 p.ill.24 cmSGSingaporeVANL000061TaraateVaibbhavVANV091912788080Springer <editore>VANV108073650ITSOL20240614RICAhttps://link.springer.com/book/10.1007/978-981-33-4642-0E-book – Accesso al full-text attraverso riconoscimento IP di Ateneo, proxy e/o ShibbolethBIBLIOTECA CENTRO DI SERVIZIO SBAVAN15NVAN0246179BIBLIOTECA CENTRO DI SERVIZIO SBA15CONS SBA EBOOK 9113 15EB 9113 20220520 ASIC design and synthesis2849475UNICAMPANIA