01373nam0 22003371i 450 SUN002218920050301120000.088-7002-552-720040826d1993 |0itac50 baitaIT|||| |||||Disturbi emotivi comuniun approccio bio-socialeDavid Goldberg, Peter Huxleya cura di Michele Tansellatraduzione di Cesare TurrinaRomaIl pensiero scientifico1993XVIII, 203 p.24 cm.001SUN00784262001 Common mental disorders1400757Depressione nervosaFISUNC008402AngosciaFISUNC009494RomaSUNL000360616.852721Goldberg, DavidSUNV0184388006Huxley, PeterSUNV018439729143Tansella, MicheleSUNV018440Turrina, CesareSUNV018441Il pensiero scientificoSUNV000063650ITSOL20181109RICASUN0022189UFFICIO DI BIBLIOTECA DEL DIPARTIMENTO DI PSICOLOGIA16 CONS 2163 16 LET6110 UFFICIO DI BIBLIOTECA DEL DIPARTIMENTO DI PSICOLOGIAIT-CE0119LET6110CONS 2163paCommon mental disorders1400757UNICAMPANIA04188nam 22006615 450 991029949450332120200701170734.03-319-03221-610.1007/978-3-319-03221-4(CKB)2670000000548027(EBL)1698118(OCoLC)880131982(SSID)ssj0001186952(PQKBManifestationID)11813525(PQKBTitleCode)TC0001186952(PQKBWorkID)11241454(PQKB)10425904(MiAaPQ)EBC1698118(DE-He213)978-3-319-03221-4(PPN)177821485(EXLCZ)99267000000054802720140321d2014 u| 0engur|n|---|||||txtccrSystem Level ESD Protection /by Vladislav Vashchenko, Mirko Scholz1st ed. 2014.Cham :Springer International Publishing :Imprint: Springer,2014.1 online resource (331 p.)Description based upon print version of record.3-319-03220-8 Includes bibliographical references and index.System 1 Level ESD design -- System Level Test Methods -- On-Chip System Level ESD Devices and Clamps -- Latch-up at System-Level Stress -- IC and Systemn ESD Co-Design.This book addresses key aspects of analog integrated circuits and systems design related to system level electrostatic discharge (ESD) protection.  It is an invaluable reference for anyone developing systems-on-chip (SoC) and systems-on-package (SoP), integrated with system-level ESD protection. The book focuses on both the design of semiconductor integrated circuit (IC) components with embedded, on-chip system level protection and IC-system co-design. The readers will be enabled to bring the system level ESD protection solutions to the level of integrated circuits, thereby reducing or completely eliminating the need for additional, discrete components on the printed circuit board (PCB) and meeting system-level ESD requirements. The authors take a systematic approach, based on IC-system ESD protection co-design. A detailed description of the available IC-level ESD testing methods is provided, together with a discussion of the correlation between IC-level and system-level ESD testing methods. The IC-level ESD protection design is demonstrated with representative case studies which are analyzed with various numerical simulations and ESD testing. The overall methodology for IC-system ESD co-design is presented as a step-by-step procedure that involves both ESD testing and numerical simulations.   • Provides a systematic approach for on-chip ESD protection design for system-level IC pins; • Describes a system-level co-design methodology, which uses external system level ESD protection components, together with on-chip ESD protection structure; • Includes a comprehensive description of wafer- level and component-level test methodologies and numerical simulations.Electronic circuitsElectronicsMicroelectronicsCircuits and Systemshttps://scigraph.springernature.com/ontologies/product-market-codes/T24068Electronic Circuits and Deviceshttps://scigraph.springernature.com/ontologies/product-market-codes/P31010Electronics and Microelectronics, Instrumentationhttps://scigraph.springernature.com/ontologies/product-market-codes/T24027Electronic circuits.Electronics.Microelectronics.Circuits and Systems.Electronic Circuits and Devices.Electronics and Microelectronics, Instrumentation.620621.381621.3815621.38152Vashchenko Vladislavauthttp://id.loc.gov/vocabulary/relators/aut861062Scholz Mirkoauthttp://id.loc.gov/vocabulary/relators/autBOOK9910299494503321System Level ESD Protection1921650UNINA