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Record Nr. |
UNISALENTO991001337469707536 |
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Autore |
Ovidius Naso, Publius |
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Titolo |
Fasti / Ovid ; with an english translation by James George Frazer ; revised by Goold |
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Pubbl/distr/stampa |
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Cambridge, Mass. ; London : Harvard University press, 2003 |
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ISBN |
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Edizione |
[Repr. with correction] |
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Descrizione fisica |
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Collana |
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Ovid ; 5 |
The Loeb classical library [Autori latini] ; 253 |
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Altri autori (Persone) |
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Frazer, James George |
Goold, George P. |
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Disciplina |
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Soggetti |
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Ovidio Nasone, Publio Fasti |
Ovidio Nasone, Publio Fasti |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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2. |
Record Nr. |
UNINA9910299571203321 |
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Autore |
Wang Zheng |
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Titolo |
High-level Estimation and Exploration of Reliability for Multi-Processor System-on-Chip / / by Zheng Wang, Anupam Chattopadhyay |
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Pubbl/distr/stampa |
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Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2018 |
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ISBN |
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Edizione |
[1st ed. 2018.] |
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Descrizione fisica |
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1 online resource (XX, 197 p. 104 illus., 72 illus. in color.) |
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Collana |
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Computer Architecture and Design Methodologies, , 2367-3486 |
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Disciplina |
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Soggetti |
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Electronic circuits |
Computers |
Electronic Circuits and Systems |
Hardware Performance and Reliability |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di bibliografia |
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Includes bibliographical references. |
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Nota di contenuto |
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Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook. |
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Sommario/riassunto |
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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures. . |
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