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Record Nr. |
UNISA996466302503316 |
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Titolo |
Applied Reconfigurable Computing [[electronic resource] ] : 15th International Symposium, ARC 2019, Darmstadt, Germany, April 9–11, 2019, Proceedings / / edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, Pedro Diniz |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
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ISBN |
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Edizione |
[1st ed. 2019.] |
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Descrizione fisica |
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1 online resource (XIII, 418 p. 217 illus., 110 illus. in color.) |
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Collana |
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Theoretical Computer Science and General Issues, , 2512-2029 ; ; 11444 |
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Disciplina |
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Soggetti |
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Computers |
Operating systems (Computers) |
Software engineering |
Computer systems |
Computers, Special purpose |
Artificial intelligence |
Computer Hardware |
Operating Systems |
Software Engineering |
Computer System Implementation |
Special Purpose and Application-Based Systems |
Artificial Intelligence |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di contenuto |
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Applications -- Fault-Tolerant Architecture for On-Board Dual-Core Synthetic-Aperture Radar Imaging -- Optimizing CNN-based Hyperspectral Image Classification on FPGAs -- Supporting Columnar In-Memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow -- A Novel Encoder for TDCs -- A Resource Reduced Application-Specific FPGA Switch -- Software-Defined FPGA Accelerator Design for Mobile Deep Learning Applications -- Partial Reconfiguration and Security -- Probabilistic Performance Modelling |
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when using Partial Reconfiguration to Accelerate Streaming Applications with Non-Deterministic Task Scheduling -- Leveraging the Partial Reconfiguration Capability of FPGAs for Processor-Based Fail-Operational Systems -- (ReCo)Fuse Your PRC or Lose Security: Finally Reliable Reconfiguration-based Countermeasures on FPGAs -- Proof-Carrying Hardware versus the Stealthy Malicious LUT Hardware Trojan -- Secure Local Configuration of Intellectual Property Without a Trusted Third Party -- Image/Video Processing -- HiFlipVX: an Open Source High-Level Synthesis FPGA Library for Image Processing -- Real-time FPGA implementation of connected component labelling for a 4K video stream -- A Scalable FPGA-based Architecture for Depth Estimation in SLAM -- High-Level Synthesis -- Evaluating LULESH Kernels on OpenCL FPGA -- The TaPaSCo Open-Source Toolflow for the Automated Composition of Task-Based Parallel Reconfigurable Computing Systems -- Graph-based Code Restructuring Targeting HLS for FPGAs -- CGRAs and Vector Processing -- UltraSynth: Integration of a CGRA into a Control Engineering Environment -- Exploiting reconfigurable vector processing for energy-efficient computation in 3D-stacked memories -- Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation for Arithmetic Algorithms -- Architectures -- ReM: a Reconfigurable Multipotent Cell for New Distributed Reconfigurable Architectures -- Update or Invalidate: Influence of Coherence Protocols on Configurable HW Accelerators -- Design Frameworks and Methodology -- Hybrid Prototyping for Manycore Design and Validation -- Evaluation of FPGA Partitioning Schemes for Time and Space Sharing of Heterogeneous Tasks -- Invited Talk -- Third Party CAD Tools for FPGA Design | A Survey of the Current Landscape -- Convolutional Neural Networks -- Filter-wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation -- Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs -- Faster Convolutional Neural Networks in Low Density FPGAs using Block Pruning. |
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Sommario/riassunto |
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This book constitutes the proceedings of the 15th International Symposium on Applied Reconfigurable Computing, ARC 2019, held in Darmstadt, Germany, in April 2019. The 20 full papers and 7 short papers presented in this volume were carefully reviewed and selected from 52 submissions. In addition, the volume contains 1 invited paper. The papers were organized in topical sections named: Applications; partial reconfiguration and security; image/video processing; high-level synthesis; CGRAs and vector processing; architectures; design frameworks and methodology; convolutional neural networks. |
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