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1. |
Record Nr. |
UNISA996465776603316 |
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Titolo |
Languages and Compilers for Parallel Computing [[electronic resource] ] : 5th International Workshop, New Haven, Connecticut, USA, August 3-5, 1992. Proceedings / / edited by Utpal Banerjee, David Gelernter, Alex Nicolau, David Padua |
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Pubbl/distr/stampa |
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Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 1993 |
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ISBN |
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Edizione |
[1st ed. 1993.] |
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Descrizione fisica |
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1 online resource (X, 586 p.) |
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Collana |
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Lecture Notes in Computer Science, , 0302-9743 ; ; 757 |
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Disciplina |
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Soggetti |
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Computers |
Architecture, Computer |
Programming languages (Electronic computers) |
Computer programming |
Arithmetic and logic units, Computer |
Computer graphics |
Computation by Abstract Devices |
Computer System Implementation |
Programming Languages, Compilers, Interpreters |
Programming Techniques |
Arithmetic and Logic Structures |
Computer Graphics |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di contenuto |
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Compilation of a highly parallel Actor-Based Language -- A concurrent execution semantics for Parallel Program Graphs and Program Dependence Graphs -- Using profile information to assist advanced compiler optimization and scheduling -- A hierarchical parallelizing compiler for VLIW/MIMD machines -- Dynamic dependence analysis: A novel method for data dependence evaluation -- On the feasibility of dynamic partitioning of pointer structures -- Compiler analysis for irregular problems in fortran D -- Data ensembles in Orca C -- |
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Compositional C++: Compositional parallel programming -- Data parallelism and Linda -- Techniques for efficient execution of fine-grained concurrent programs -- Computing per-process summary side-effect information -- Supporting SPMD execution for dynamic data structures -- Determining transformation sequences for loop parallelization -- Compiler optimizations for massively parallel machines: Transformations on iterative spatial loops -- Handling distributed data in Vienna Fortran procedures -- On the synthesis of parallel programs from tensor product formulas for block recursive algorithms -- Collective loop fusion for array contraction -- Parallel hybrid data flow algorithms: A case study -- A control-parallel programming model implemented on SIMD hardware -- C**: A large-grain, object-oriented, data-parallel programming language -- A calculus of gamma programs -- A Linda-based runtime system for a distributed logic language -- Parallelizing a C Dialect for distributed memory MIMD machines -- A singular loop transformation framework based on non-singular matrices -- Designing the McCAT compiler based on a family of structured intermediate representations -- Doany: Not just another parallel loop -- Data dependence and data-flow analysis of arrays -- Experience with techniques for refining data race detection -- Extending the Banerjee-Wolfe test to handle execution conditions -- A FORTRAN compiling method for dataflow machines and its prototype compiler for the parallel processing system-Harray -- Distributed slicing and partial re-execution for distributed programs -- A program's eye view of Miprac -- Symbolic program analysis and optimization for parallelizing compilers -- Utilizing new communication features in compilation for private-memory machines. |
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Sommario/riassunto |
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The articles in this volume are revised versions of the best papers presented at the Fifth Workshop on Languages and Compilers for Parallel Computing, held at Yale University, August 1992. The previous workshops in this series were held in Santa Clara (1991), Irvine (1990), Urbana (1989), and Ithaca (1988). As in previous years, a reasonable cross-section of some of the best work in the field is presented. The volume contains 35 papers, mostly by authors working in the U.S. or Canada but also by authors from Austria, Denmark, Israel, Italy, Japan and the U.K. |
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2. |
Record Nr. |
UNISA996465608603316 |
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Titolo |
Languages and Compilers for Parallel Computing [[electronic resource] ] : 22nd International Workshop, LCPC 2009, Newark, DE, USA, October 8-10, 2009, Revised Selected Papers / / edited by Guang R. Gao, Lori Pollock, John Cavazos, Xiaoming Li |
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Pubbl/distr/stampa |
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Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2010 |
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ISBN |
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1-280-38685-1 |
9786613564771 |
3-642-13374-6 |
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Edizione |
[1st ed. 2010.] |
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Descrizione fisica |
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1 online resource (XI, 426 p. 186 illus.) |
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Collana |
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Theoretical Computer Science and General Issues, , 2512-2029 ; ; 5898 |
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Disciplina |
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Soggetti |
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Compilers (Computer programs) |
Computer programming |
Computer networks |
Artificial intelligence—Data processing |
Artificial intelligence |
Computer science |
Compilers and Interpreters |
Programming Techniques |
Computer Communication Networks |
Data Science |
Artificial Intelligence |
Models of Computation |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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A Communication Framework for Fault-Tolerant Parallel Execution -- The STAPL pList -- Hardware Support for OpenMP Collective Operations -- Loop Transformation Recipes for Code Generation and Auto-Tuning -- MIMD Interpretation on a GPU -- TL-DAE: Thread-Level Decoupled Access/Execution for OpenMP on the Cyclops-64 Many-Core Processor -- Mapping Streaming Languages to General Purpose Processors |
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through Vectorization -- A Balanced Approach to Application Performance Tuning -- Automatically Tuning Parallel and Parallelized Programs -- DFT Performance Prediction in FFTW -- Safe and Familiar Multi-core Programming by Means of a Hybrid Functional and Imperative Language -- Hierarchical Place Trees: A Portable Abstraction for Task Parallelism and Data Movement -- OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers -- Programming with Intervals -- Adaptive and Speculative Memory Consistency Support for Multi-core Architectures with On-Chip Local Memories -- Synchronization-Free Automatic Parallelization: Beyond Affine Iteration-Space Slicing -- Automatic Data Distribution for Improving Data Locality on the Cell BE Architecture -- Automatic Restructuring of Linked Data Structures -- Using the Meeting Graph Framework to Minimise Kernel Loop Unrolling for Scheduled Loops -- Efficient Tiled Loop Generation: D-Tiling -- Effective Source-to-Source Outlining to Support Whole Program Empirical Optimization -- Speculative Optimizations for Parallel Programs on Multicores -- Fastpath Speculative Parallelization -- PSnAP: Accurate Synthetic Address Streams through Memory Profiles -- Enforcing Textual Alignment of Collectives Using Dynamic Checks -- A Code Generation Approach for Auto-Vectorization in the Spade Compiler -- Portable Just-in-Time Specialization of Dynamically Typed Scripting Languages -- Reducing Training Time in a One-Shot Machine Learning-Based Compiler -- Optimizing Local Memory Allocation and Assignment through a Decoupled Approach -- Unrolling Loops Containing Task Parallelism. |
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Sommario/riassunto |
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Itisourpleasuretopresentthepapersacceptedforthe22ndInternationalWo- shop on Languages and Compilers for Parallel Computing held during October 8–10 2009 in Newark Delaware, USA. Since 1986, LCPC has became a valuable venueforresearchersto reportonworkinthegeneralareaofparallelcomputing, high-performance computer architecture and compilers. LCPC 2009 continued this tradition and in particular extended the area of interest to new parallel computing accelerators such as the IBM Cell Processor and Graphic Processing Unit (GPU). This year we received 52 submissions from 15 countries. Each submission receivedatleastthreereviewsandmosthadfour.ThePCalsosoughtadditional externalreviewsforcontentiouspapers.ThePCheldanall-dayphoneconference on August 24 to discuss the papers. PC members who had a con?ict of interest were asked to leave the call temporarily when the corresponding papers were discussed. From the 52 submissions, the PC selected 25 full papers and 5 short paperstobeincludedintheworkshopproceeding,representinga58%acceptance rate. We were fortunate to have three keynote speeches, a panel discussion and a tutorial in this year’s workshop. First, Thomas Sterling, Professor of Computer Science at Louisiana State University, gave a keynote talk titled “HPC in Phase Change: Towards a New Parallel Execution Model.” Sterling argued that a new multi-dimensional research thrust was required to realize the design goals with regard to power, complexity, clock rate and reliability in the new parallel c- puter systems.ParalleX,anexploratoryexecutionmodeldevelopedbySterling’s group was introduced to guide the co-design of new architectures, programming methods and system software. |
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