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1. |
Record Nr. |
UNISA996465679003316 |
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Titolo |
Computers Helping People with Special Needs [[electronic resource] ] : 16th International Conference, ICCHP 2018, Linz, Austria, July 11-13, 2018, Proceedings, Part II / / edited by Klaus Miesenberger, Georgios Kouroupetroglou |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018 |
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ISBN |
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Edizione |
[1st ed. 2018.] |
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Descrizione fisica |
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1 online resource (XXX, 568 p. 180 illus.) |
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Collana |
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Information Systems and Applications, incl. Internet/Web, and HCI ; ; 10897 |
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Disciplina |
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Soggetti |
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User interfaces (Computer systems) |
Application software |
Special purpose computers |
Computer communication systems |
Artificial intelligence |
Education—Data processing |
User Interfaces and Human Computer Interaction |
Information Systems Applications (incl. Internet) |
Special Purpose and Application-Based Systems |
Computer Communication Networks |
Artificial Intelligence |
Computers and Education |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Sommario/riassunto |
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The two-volume set LNCS 10896 and 10897 constitutes the refereed proceedings of the 16th International Conference on Computers Helping People with Special Needs, ICCHP 2018, held in Linz, Austria, in July 2018. The 101 revised full papers and 78 short papers presented were carefully reviewed and selected from 356 submissions. The papers are organized in the following topical sections: Web accessibility |
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in the connected world; accessibility and usability of mobile platforms for people with disabilities and elderly persons: design, development and engineering; accessible system/information/document design; accessible e-learning - e-learning for accessibility/AT; personalized access to TV, film, theatre, and music; digital games accessibility; accessibility and usability of self-service terminals, technologies and systems; universal learning design; motor and mobility disabilities: AT, HCI, care; empowerment of people with cognitive disabilities using digital technologies; augmented and alternative communication (AAC), supported speech; Art Karshmer lectures in access to mathematics, science and engineering; environmental sensing technologies for visual impairment; 3D printing in the domain of assistive technologies (AT) and do it yourselves (DIY) AT; tactile graphics and models for blind people and recognition of shapes by touch; access to artworks and its mediation by and for visually impaired people; digital navigation for people with visual impairments; low vision and blindness: human computer interaction; future perspectives for ageing well: AAL tools, products, services; mobile healthcare and m-health apps for people with disabilities; and service and information provision. |
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2. |
Record Nr. |
UNISA996465860903316 |
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Titolo |
Correct Hardware Design and Verification Methods [[electronic resource] ] : 13th IFIP WG 10.5Advanced Research, Working Conference, CHARME 2005, Saarbrücken, Germany, October 3-6, 2005, Proceedings / / edited by Dominique Borrione, Wolfgang Paul |
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Pubbl/distr/stampa |
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Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2005 |
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Edizione |
[1st ed. 2005.] |
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Descrizione fisica |
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1 online resource (XII, 414 p.) |
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Collana |
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Theoretical Computer Science and General Issues, , 2512-2029 ; ; 3725 |
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Disciplina |
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Soggetti |
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Computer science |
Computers |
Software engineering |
Machine theory |
Artificial intelligence |
Theory of Computation |
Computer Hardware |
Computer Science Logic and Foundations of Programming |
Software Engineering |
Formal Languages and Automata Theory |
Artificial Intelligence |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Invited Talks -- Is Formal Verification Bound to Remain a Junior Partner of Simulation? -- Verification Challenges in Configurable Processor Design with ASIP Meister -- Tutorial -- Towards the Pervasive Verification of Automotive Systems -- Functional Approaches to Design Description -- Wired: Wire-Aware Circuit Design -- Formalization of the DE2 Language -- Game Solving Approaches -- Finding and Fixing Faults -- Verifying Quantitative Properties Using Bound Functions -- Abstraction -- How Thorough Is Thorough Enough? -- Interleaved Invariant Checking with Dynamic Abstraction -- Automatic Formal Verification of Liveness for Pipelined Processors with Multicycle |
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Functional Units -- Algorithms and Techniques for Speeding (DD-Based) Verification 1 -- Efficient Symbolic Simulation via Dynamic Scheduling, Don’t Caring, and Case Splitting -- Achieving Speedups in Distributed Symbolic Reachability Analysis Through Asynchronous Computation -- Saturation-Based Symbolic Reachability Analysis Using Conjunctive and Disjunctive Partitioning -- Real Time and LTL Model Checking -- Real-Time Model Checking Is Really Simple -- Temporal Modalities for Concisely Capturing Timing Diagrams -- Regular Vacuity -- Algorithms and Techniques for Speeding Verification 2 -- Automatic Generation of Hints for Symbolic Traversal -- Maximal Input Reduction of Sequential Netlists via Synergistic Reparameterization and Localization Strategies -- A New SAT-Based Algorithm for Symbolic Trajectory Evaluation -- Evaluation of SAT-Based Tools -- An Analysis of SAT-Based Model Checking Techniques in an Industrial Environment -- Model Reduction -- Exploiting Constraints in Transformation-Based Verification -- Identification and Counter Abstraction for Full Virtual Symmetry -- Verification of Memory Hierarchy Mechanisms -- On the Verification of Memory Management Mechanisms -- Counterexample Guided Invariant Discovery for Parameterized Cache Coherence Verification -- Short Papers -- Symbolic Partial Order Reduction for Rule Based Transition Systems -- Verifying Timing Behavior by Abstract Interpretation of Executable Code -- Behavior-RTL Equivalence Checking Based on Data Transfer Analysis with Virtual Controllers and Datapaths -- Deadlock Prevention in the Æthereal Protocol -- Acceleration of SAT-Based Iterative Property Checking -- Error Detection Using BMC in a Parallel Environment -- Formal Verification of Synchronizers -- A Parameterized Benchmark Suite of Hard Pipelined-Machine-Verification Problems -- Improvements to the Implementation of Interpolant-Based Model Checking -- High-Level Modelling, Analysis, and Verification on FPGA-Based Hardware Design -- Proving Parameterized Systems: The Use of Pseudo-Pipelines in Polyhedral Logic -- Resolving Quartz Overloading -- FPGA Based Accelerator for 3-SAT Conflict Analysis in SAT Solvers -- Predictive Reachability Using a Sample-Based Approach -- Minimizing Counterexample of ACTL Property -- Data Refinement for Synchronous System Specification and Construction -- Introducing Abstractions via Rewriting -- A Case Study: Formal Verification of Processor Critical Properties. |
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3. |
Record Nr. |
UNINA9910484433703321 |
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Titolo |
Job Scheduling Strategies for Parallel Processing : 12th International Workshop, JSSPP 2006, Saint-Malo, France, June 26, 2006, Revised Selected Papers / / edited by Eitan Frachtenberg, Uwe Schwiegelshohn |
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Pubbl/distr/stampa |
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Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007 |
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ISBN |
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1-280-90221-3 |
9786610902217 |
3-540-71035-3 |
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Edizione |
[1st ed. 2007.] |
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Descrizione fisica |
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1 online resource (VIII, 264 p.) |
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Collana |
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Theoretical Computer Science and General Issues, , 2512-2029 ; ; 4376 |
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Disciplina |
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Soggetti |
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Computer systems |
Operating systems (Computers) |
Computer programming |
Algorithms |
Microprocessors |
Computer architecture |
Logic design |
Computer System Implementation |
Operating Systems |
Programming Techniques |
Processor Architectures |
Logic Design |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Provably Efficient Two-Level Adaptive Scheduling -- Scheduling Dynamically Spawned Processes in MPI-2 -- Advance Reservation Policies for Workflows -- On Advantages of Scheduling Using Genetic Fuzzy Systems -- Moldable Parallel Job Scheduling Using Job Efficiency: An Iterative Approach -- Adaptive Job Scheduling Via Predictive Job Resource Allocation -- A Data Locality Aware Online Scheduling Approach for I/O-Intensive Jobs with File Sharing -- Volunteer |
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Computing on Clusters -- Load Balancing: Toward the Infinite Network and Beyond -- Symbiotic Space-Sharing on SDSC’s DataStar System -- Modeling Job Arrivals in a Data-Intensive Grid -- On Grid Performance Evaluation Using Synthetic Workloads. |
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Sommario/riassunto |
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This book constitutes the thoroughly refereed postproceedings of the 12th International Workshop on Job Scheduling Strategies for Parallel Processing, JSSPP 2006, held in Saint-Malo, France, in June 2006 in conjunction with the Joint International Conference on Measurement and Modeling of Computer Systems SIGMETRICS/Performance 2006. The 12 revised full research papers presented went through two rounds of reviewing and improvement. The papers cover all current issues of job scheduling strategies for parallel processing such as workflow problems, scheduling performance, job migration issues, performance degradation by resource sharing, and job modeling issues in grid computing. |
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4. |
Record Nr. |
UNIORUON00497546 |
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Autore |
Paris, Gaston |
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Titolo |
Esquisse historique de la littérature française au Moyen Age : (depuis les origines jusqu'à la fin du 15. siècle) / G. Paris |
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Pubbl/distr/stampa |
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Edizione |
[2. ed] |
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Descrizione fisica |
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Disciplina |
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Soggetti |
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Letteratura francese - Medioevo |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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