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Record Nr. |
UNISA996418302503316 |
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Autore |
Lutsyk Petro |
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Titolo |
A Pipelined Multi-Core Machine with Operating System Support [[electronic resource] ] : Hardware Implementation and Correctness Proof / / by Petro Lutsyk, Jonas Oberhauser, Wolfgang J. Paul |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
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ISBN |
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Edizione |
[1st ed. 2020.] |
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Descrizione fisica |
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1 online resource (634 pages) |
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Collana |
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Theoretical Computer Science and General Issues, , 2512-2029 ; ; 9999 |
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Disciplina |
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Soggetti |
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Computer programming |
Computer engineering |
Computer networks |
Microprogramming |
Computer input-output equipment |
Logic programming |
Computer science |
Programming Techniques |
Computer Engineering and Networks |
Control Structures and Microprogramming |
Input/Output and Data Communications |
Logic in AI |
Theory of Computation |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di contenuto |
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Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic. |
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Sommario/riassunto |
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This work is building on results from the book named “A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness” |
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by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk . |
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