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Record Nr. |
UNISA996280555203316 |
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Titolo |
IEEE Std 1364.1-2002 : IEEE Standard for Verilog Register Transfer Level Synthesis / / Institute of Electrical and Electronics Engineers (IEEE) |
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Pubbl/distr/stampa |
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New York : , : Institute of Electrical and Electronics Engineers (IEEE), , 2002 |
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ISBN |
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Descrizione fisica |
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1 online resource (vii, 100 pages) |
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Disciplina |
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Soggetti |
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Verilog (Computer hardware description language) |
Verilog (Computer hardware description language) - Standards |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Sommario/riassunto |
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Standard syntax and semantics for Verilog HDL-based RTL synthesis are described in this standard. |
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