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1. |
Record Nr. |
UNINA9910452771303321 |
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Autore |
Siddique Osama |
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Titolo |
Pakistan's experience with formal law : an alien justice / / Osama Siddique [[electronic resource]] |
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Pubbl/distr/stampa |
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Cambridge : , : Cambridge University Press, , 2013 |
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ISBN |
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1-139-89182-0 |
1-107-25133-8 |
1-107-25050-1 |
1-107-24801-9 |
1-107-24884-1 |
1-139-81450-8 |
1-107-24967-8 |
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Descrizione fisica |
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1 online resource (xvii, 469 pages) : digital, PDF file(s) |
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Collana |
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Cambridge studies in law and society |
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Disciplina |
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Soggetti |
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Justice, Administration of - Pakistan |
Law reform - Pakistan |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Title from publisher's bibliographic system (viewed on 05 Oct 2015). |
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Nota di contenuto |
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The hegemony of heritage : the "narratives of colonial displacement" : the absence of the past in Pakistani reform narratives -- Law in practice : the Lahore District Courts survey (2010-2011) -- Law, crime, context and vulnerability : the Punjab crime perception survey (2009-2010) -- Approaches to legal and judicial reform in Pakistan : post colonial inertia and the paucity of imagination in times of turmoil and change -- Reform on paper : a post mortem of justice sector reform in Pakistan from 1998-2010 -- Reform nirvanas and reality checks : justice sector reform in Pakistan in the twenty-first century and the monopoly of the "experts" -- Towards a new approach. |
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Sommario/riassunto |
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Law reform in Pakistan attracts such disparate champions as the Chief Justice of Pakistan, the USAID and the Taliban. Common to their equally obsessive pursuit of 'speedy justice' is a remarkable obliviousness to the historical, institutional and sociological factors that alienate Pakistanis from their formal legal system. This pioneering book highlights vital and widely neglected linkages between the 'narratives of |
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colonial displacement' resonant in the literature on South Asia's encounter with colonial law and the region's postcolonial official law reform discourses. Against this backdrop, it presents a typology of Pakistani approaches to law reform and critically evaluates the IFI-funded single-minded pursuit of 'efficiency' during the last decade. Employing diverse methodologies, it proceeds to provide empirical support for a widening chasm between popular, at times violently expressed, aspirations for justice and democratically deficient reform designed in distant IFI headquarters that is entrusted to the exclusive and unaccountable Pakistani 'reform club'. |
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2. |
Record Nr. |
UNISA996199541903316 |
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Titolo |
2005 IEEE International High Level Design Validation and Test Workshop |
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Pubbl/distr/stampa |
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[Place of publication not identified], : I E E E, 2005 |
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ISBN |
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Descrizione fisica |
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1 online resource (viii, 250 pages) : illustrations |
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Disciplina |
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Soggetti |
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Computer software - Verification |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di contenuto |
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Simulation-based functional test generation for embedded processors,"C. -- Scalable defect mapping and configuration of memory-based nanofabrics,"Chen -- Improvement of fault injection techniques based on VHDL code modification,"J. -- MVP: a mutation-based validation paradigm,"J. -- Establishing latch correspondence for embedded circuits of PowerPC microprocessors,"H. -- Sequential equivalence checking based on k-th invariants and circuit SAT solving,"Feng -- VERISEC: verifying equivalence of sequential circuits using SAT,"M. -- Automated clock inference for stream function-based system level specifications,"J. -- Cosimulation of ITRON-based embedded software with SystemC,"S. -- A software test program generator for verifying system-on-chips,"A. -- Stimulus generation for interface protocol |
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verification using the nondeterministic extended finite state machine model,"Che-Hua -- DVGen: a test generator for the transmeta Efficeon VLIW processor,"K. -- Reuse in system-level stimuli-generation,"Y. -- Harnessing machine learning to improve the success rate of stimuli generation,"S. -- A new simulation-based property checking algorithm based on partitioned alternative search space traversal,"Qingwei -- Validating families of latency insensitive protocols,"S. -- GASIM: a fast Galois field based simulator for functional model,"D. -- Overlap reduction in symbolic system traversal,"P. -- Formal verification of high-level conformance with symbolic simulation,"R. -- A method for generation of GSTE assertion graphs,"E. -- Automatic abstraction refinement for Petri nets verification,"Zhenyu -- An optimum algorithm for compacting error traces for efficient functional debugging,"Chia-Chih -- Increasing the deducibility in CNF instances for efficient SAT-based bounded model checking,"V. -- B-cubing theory: new possibilities for efficient SAT-solving,"D. -- Multilevel design validation in a secure embedded system,"D. -- Security evaluation against electromagnetic analysis at design time,"Huiyun -- Formal meaning of coverage metrics in simulation-based hardware design verification,"I. -- Advanced analysis techniques for cross-product coverage,"H. -- A proof of correctness for the construction of property monitors,". |
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