System-on-chip test architectures : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba

• Record Nr.: UNINA9910971902703321
• Autore: Wang Laung-Terng
• Pubbl/distr/stampa: Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008; Elsevier, [2007]
• ISBN: 1-281-10004-8; 9786611100049; 0-08-055680-9
• Edizione: [1st ed.]
• Descrizione fisica: 1 online resource (893 p.)
• Collana: The Morgan Kaufmann series in systems on silicon
• Altri autori (Persone): WangLaung-Terng; StroudCharles E; ToubaNur A
• Disciplina: 621.39/5
• Soggetti: Systems on a chip - Testing; Integrated circuits - Very large scale integration - Testing; Integrated circuits - Very large scale integration - Design
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Description based upon print version of record.
• Nota di bibliografia: Includes bibliographical references and index.
• Nota di contenuto: Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard); 1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan ; Design; 2.2.1.3 LSSD Scan Design; 2.2.1.4 Enhanced-Scan Design; 2.2.2 Low-Power Scan Architectures; 2.2.2.1 Reduced-Voltage Low-Power Scan Design2.2.2.2 Reduced-Frequency Low-Power Scan Design; 2.2.2.3 Multi-Phase or Multi-Duty Low-Power Scan Design; 2.2.2.4 Bandwidth-Matching Low-Power Scan Design; 2.2.2.5 Hybrid Low-Power Scan Design; 2.2.3 At-Speed Scan Architectures; 2.3 Logic Built-In Self-Test; 2.3.1 Logic BIST Architectures; 2.3.1.1 Self-Testing Using MISR and Parallel SRSG (STUMPS); 2.3.1.2 Concurrent Built-In Logic Block Observer (CBILBO); 2.3.2 Coverage-Driven Logic BIST Architectures; 2.3.2.1 Weighted Pattern Generation; 2.3.2.2 Test Point Insertion; 2.3.2.3 Mixed-Mode BIST; 2.3.2.4 Hybrid BIST2.3.3 Low-Power Logic BIST Architectures; 2.3.3.1 Low-Transition BIST Design; 2.3.3.2 Test-Vector-Inhibiting BIST Design; 2.3.3.3 Modified LFSR Low-Power BIST Design; 2.3.4 At-Speed Logic BIST Architectures; 2.3.4.1 Single-Capture; 2.3.4.2 Skewed-Load; 2.3.4.3 Double-Capture; 2.3.5 Industry Practices; 2.4 Test Compression; 2.4.1 Circuits for Test Stimulus Compression; 2.4.1.1 Linear-Decompression-Based Schemes; 2.4.1.2 Broadcast-Scan-Based Schemes; 2.4.1.3 Comparison; 2.4.2 Circuits for Test Response Compaction; 2.4.2.1 Space Compaction; 2.4.2.2 Time Compaction; 2.4.2.3 Mixed Time and Space Compaction2.4.3 Low-Power Test Compression Architectures; 2.4.4 Industry Practices; 2.5 Random-Access Scan Design; 2.5.1 Random-Access Scan Architectures; 2.5.1.1 Progressive Random-Access Scan Design; 2.5.1.2 Shift-Addressable Random-Access Scan Design; 2.5.2 Test Compression RAS Architectures; 2.5.3 At-Speed RAS Architectures; 2.6 Concluding Remarks; 2.7 Exercises; Acknowledgments; References; Chapter 3 Fault-Tolerant Design; 3.1 Introduction; 3.2 Fundamentals of Fault Tolerance; 3.2.1 Reliability; 3.2.2 Mean Time to Failure (MTTF); 3.2.3 Maintainability; 3.2.4 Availability
• Sommario/riassunto: Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master qu

Managing construction logistics / / Gary Sullivan, Stephen Barthorpe, Stephen Robbins

• Record Nr.: UNINA9911137425703321
• Autore: Sullivan Gary <1959->
• Pubbl/distr/stampa: Chichester, West Sussex, U.K. ; ; Ames, Iowa, : Blackwell, c2010
• ISBN: 1-282-68742-5; 9786612687426; 1-4443-2339-3
• Edizione: [1st ed.]
• Descrizione fisica: 1 online resource (305 p.)
• Altri autori (Persone): BarthorpeStephen; RobbinsStephen <1979->
• Disciplina: 624.068/7
• Soggetti: Building - Superintendence - Data processing; Construction industry - Management - Data processing; Business logistics - Data processing; Production scheduling - Data processing
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Description based upon print version of record.
• Nota di bibliografia: Includes bibliographical references and index.
• Nota di contenuto: section 1. Contextualising logistics for construction -- section 2. Construction logistics in practice -- section 3. The future of construction logistics.
• Sommario/riassunto: Every major industry except construction uses logistics to improve its bottom line... Poor logistics is costing the construction industry at least £3 billion a year according to a report - 'Improving Construction Logistics' - published by the Strategic Forum for Construction. Additional costs arise as a result of operatives waiting for materials, and skilled craftsmen being used for unskilled jobs. Inadequate management of logistics also has an adverse effect on quality, causes delays to projects, and adds to the health and safety risks on site. This practical book highlights the b