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1. |
Record Nr. |
UNINA9910706728203321 |
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Titolo |
The Border Security, Economic Opportunity, and Immigration Modernization Act, S. 744 : hearing before the Committee on the Judiciary, United States Senate, One Hundred Thirteenth Congress, first session, April 22 and 23, 2013 |
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Pubbl/distr/stampa |
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Washington : , : U.S. Government Publishing Office, , 2018 |
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Descrizione fisica |
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1 online resource (vi, 706 pages) : illustrations |
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Collana |
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Soggetti |
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Emigration and immigration law - United States |
Border security - Law and legislation - United States |
Legislative hearings. |
United States Emigration and immigration Economic aspects |
United States Emigration and immigration Government policy |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Paper version available for sale by the Superintendent of Documents, United States Government Publishing Office. |
"Serial no. J-113-15." |
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Nota di bibliografia |
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Includes bibliographical references. |
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2. |
Record Nr. |
UNINA9911019641703321 |
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Autore |
Voldman Steven H |
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Titolo |
Latchup / / Steven H. Voldman |
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Pubbl/distr/stampa |
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Chichester, West Sussex, England ; ; Hoboken, NJ, : John Wiley, c2007 |
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ISBN |
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9786611318161 |
9781281318169 |
1281318167 |
9780470516171 |
0470516178 |
9780470516164 |
047051616X |
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Descrizione fisica |
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1 online resource (474 p.) |
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Disciplina |
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Soggetti |
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Metal oxide semiconductors, Complementary - Defects |
Metal oxide semiconductors, Complementary - Reliability |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Latchup; Contents; About the Author; Preface; Acknowledgements; 1 CMOS Latchup; 1.1 CMOS LATCHUP; 1.1.1 CMOS Latchup-What is Latchup?; 1.1.2 CMOS Latchup-Why is Latchup Still an Issue ?; 1.1.3 Early CMOS Latchup History; 1.2 FUNDAMENTAL CONCEPTS OF LATCHUP DESIGN PRACTICE; 1.3 BUILDING A CMOS LATCHUP STRATEGY; 1.3.1 Building a CMOS Business Strategy - 18 Steps in Building a CMOS Latchup Business Strategy; 1.3.2 Building a CMOS Latchup Technology Strategy - 18 Steps in Building a CMOS Latchup Technology Strategy; 1.4 CMOS LATCHUP TECHNOLOGY MIGRATION STRATEGY |
1.5 KEY METRICS OF LATCHUP DESIGN PRACTICE1.6 CMOS LATCHUP TECHNOLOGY TRENDS AND SCALING; 1.7 KEY DEVELOPMENTS; 1.7.1 Key Innovations; 1.7.2 Key Contributions; 1.7.3 Key Patents; 1.8 LATCHUP FAILURE MECHANISMS; 1.9 CMOS LATCHUP EVENTS; 1.9.1 Power-Up Sequence Initiated Latchup; 1.9.2 Input Pin Overshoot and Power-Up Sequence Initiated Latchup; 1.9.3 Input Pin Undershoot and Power-Up Sequence Initiated Latchup; 1.9.4 Multiple Power Supply |
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Power-Up Sequence Initiated Latchup; 1.9.5 Power Supply Overshoot Initiated Latchup; 1.9.6 Power Supply Undershoot Initiated Latchup |
1.9.7 Power Supply (Ground Rail) Undershoot Initiated Latchup1.10 ELECTROSTATIC DISCHARGE SOURCES; 1.10.1 Human Body Model ESD Event; 1.10.2 Machine Model ESD Event; 1.10.3 Cable Discharge Event Source; 1.11 SINGLE EVENT LATCHUP; 1.11.1 High-Energy Photon Emissions; 1.11.2 Alpha Particle Ionizing Source; 1.11.3 Cosmic Ray Source; 1.11.4 Heavy Ion Source; 1.12 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 Bipolar Transistors; 2.1 THE BIPOLAR TRANSISTOR AND CMOS LATCHUP; 2.1.1 Fundamental Equations of Semiconductors and the Drift-Diffusion Current Constitutive Relationships |
2.1.2 Diode Forward Bias Conditions2.1.3 Diode Forward Bias Conditions and High-level Injection; 2.2 BIPOLAR TRANSISTOR; 2.2.1 Bipolar Current Gain; 2.2.2 Bipolar Collector-to-Emitter Transport Factor; 2.2.3 Bipolar Current Characteristics; 2.2.4 Bipolar Model Gummel Plot; 2.2.5 Bipolar Current Model-Ebers-Moll Model; 2.2.6 Bipolar Transistor Base Defect; 2.2.7 Bipolar Transistor Emitter Defect; 2.2.8 Bipolar Base Current - Base Defect and Emitter Defect Relation to Bipolar Current Gain; 2.3 RECOMBINATION MECHANISMS; 2.3.1 Shockley-Read-Hall (SRH) Generation-Recombination Model |
2.3.2 Auger Recombination Model2.3.3 Surface Recombination Mechanisms; 2.3.4 Surface Recombination Velocity; 2.3.5 Recombination Mechanisms and Neutron Irradiation; 2.3.6 Recombination Mechanisms and Gold Recombination Centers; 2.4 PHOTON CURRENTS IN METALLURGICAL JUNCTIONS; 2.5 AVALANCHE BREAKDOWN; 2.5.1 Bipolar Transistor Breakdown; 2.5.2 MOSFET Avalanche Breakdown; 2.6 VERTICAL BIPOLAR TRANSISTOR MODEL; 2.7 LATERAL BIPOLAR TRANSISTOR MODELS; 2.7.1 Lindmayer-Schneider Model; 2.7.2 Bipolar Current Gain with Lateral and Vertical Contributions |
2.7.3 Lateral Bipolar Transistor Models - Nonfield-Assisted |
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Sommario/riassunto |
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Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cabl |
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