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Record Nr. |
UNINA9910983362803321 |
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Titolo |
Emerging VLSI Devices, Circuits and Architectures : Proceedings of the 27th International Symposium, VDAT 2023 / / edited by Anu Gupta, Jai Gopal Pandey, Nitin Chaturvedi, Devesh Dwivedi |
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Pubbl/distr/stampa |
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Singapore : , : Springer Nature Singapore : , : Imprint : Springer, , 2025 |
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ISBN |
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Edizione |
[1st ed. 2025.] |
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Descrizione fisica |
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1 online resource (XX, 350 p. 296 illus., 200 illus. in color.) |
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Collana |
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Lecture Notes in Electrical Engineering, , 1876-1119 ; ; 1234 |
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Disciplina |
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Soggetti |
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Electronic circuits |
Computer engineering |
Computer networks |
Electronic Circuits and Systems |
Computer Engineering and Networks |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Analysis of SQNR Degradation in Noise-Shaped SAR Analog-to-Digital Converters at High Input Signal Amplitudes -- An improved clock booster circuit suitable for boost converters in energy harvesting environments -- A Current-Mode-Logic Based PFD-Charge Pump Circuit for Low Reference Spur PLLs -- An Energy Efficient Mixed Logic 2-to-4 Decoder for Embedded Memory Applications -- Analysis and Modeling of Self-Heating and Substrate Induced Transitions in 5 nm Stacked Nanosheet FET -- Chemisorption Analysis of NOx Sensor Using NF/Pr-AGNR: A DFT Investigation -- Design and Analysis of Differential Configuration based Active Inductor for 5G Sub-6GHz Applications -- A Dual-Mode High-Frequency Grounded Memristor Emulator Circuit -- Demonstration of Doped-HfO2 Ferroelectric based Double Layer Stacked NC FinFET -- High Precision Programmable Thermistor Linearization ASIC for Electro-Optical Payload Applications -- Design and Analysis of Low-Power Protection Circuits for LDO Regulators -- Preventing Costly Iterations by Delivering SoC Congestion Aware Standard Cell Lib using Pin Accessibility Checker -- High Throughput |
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Multiple Device Diagnosis System for Hierarchical Test Designs -- Characterization of Multi-Vt Transistors for Analog IC Design in Sub-nanometer Technologies -- Design and Analysis of Modified Strong Arm Latch Comparator with Reduced Kickback Noise -- Construction of non-rectangular floor plans for properly triangulated planar graphs. |
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Sommario/riassunto |
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This book constitutes the proceedings of the 27th International Symposium on VLSI Design and Test, VDAT 2023. The 32 regular papers and 16 short papers presented in this book are carefully reviewed and selected from 220 submissions. They are organized in topical sections as follows: Low-Power Integrated Circuits and Devices; FPGA-Based Design and Embedded Systems; Memory, Computing, and Processor Design; CAD for VLSI; Emerging Integrated Circuits and Systems; VLSI Testing and Security; and System-Level Design. |
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