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Record Nr. |
UNINA9910872648603321 |
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Titolo |
Multiple-Valued Logic: ISMVL '98 |
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Pubbl/distr/stampa |
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[Place of publication not identified], : I E E E Imprint, 1998 |
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Descrizione fisica |
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Disciplina |
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Soggetti |
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Many-valued logic |
Switching theory |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di contenuto |
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Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138) -- Table of contents -- Advanced circuit technology to realize post giga-bit DRAM -- Development of InGaAs-based multiple-junction surface tunnel transistors for multiple-valued logic circuits -- Ultrafast ternary quantizer using resonant tunneling devices -- A Josephson ternary memory circuit -- A note on realizing multiple-valued logic functions using Akers' cells-cell sizes and path lengths -- Minimization of exclusive sums of multi-valued complex terms for logic cell arrays -- Minimal test set generation for fault diagnosis in R-valued PLAs. |
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