Fundamentals of computer organization and architecture / / Mostafa Abd-El-Barr, Hesham El-Rewini

• Record Nr.: UNINA9910819129403321
• Autore: Abd-El-Barr Mostafa <1950->
• Pubbl/distr/stampa: Hoboken, N.J., : Wiley, c2005
• ISBN: 9786610252381; 9781280252389; 1280252383; 9780470321959; 0470321954; 9780471478331; 0471478334; 9780471478324; 0471478326
• Edizione: [1st ed.]
• Descrizione fisica: 1 online resource (289 p.)
• Collana: Wiley series on parallel and distributed computing
• Altri autori (Persone): El-RewiniHesham
• Disciplina: 004.2/2
• Soggetti: Computer architecture; Parallel processing (Electronic computers)
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Description based upon print version of record.
• Nota di bibliografia: Includes bibliographical references (p. 256-257) and index.
• Nota di contenuto: FUNDAMENTALS OF COMPUTER ORGANIZATION AND ARCHITECTURE; CONTENTS; Preface; 1. Introduction to Computer Systems; 1.1. Historical Background; 1.2. Architectural Development and Styles; 1.3. Technological Development; 1.4. Performance Measures; 1.5. Summary; Exercises; References and Further Reading; 2. Instruction Set Architecture and Design; 2.1. Memory Locations and Operations; 2.2. Addressing Modes; 2.3. Instruction Types; 2.4. Programming Examples; 2.5. Summary; Exercises; References and Further Reading; 3. Assembly Language Programming; 3.1. A Simple Machine; 3.2. Instructions Mnemonics and Syntax3.3. Assembler Directives and Commands; 3.4. Assembly and Execution of Programs; 3.5. Example: The X86 Family; 3.6. Summary; Exercises; References and Further Reading; 4. Computer Arithmetic; 4.1. Number Systems; 4.2. Integer Arithmetic; 4.3 Floating-Point Arithmetic; 4.4 Summary; Exercises; ; References and Further Reading; 5. Processing Unit Design; 5.1. CPU Basics; 5.2. Register Set; 5.3. Datapath; 5.4. CPU Instruction Cycle; 5.5. Control Unit; 5.6. Summary; Exercises; References; 6. Memory System Design I; 6.1. Basic Concepts; 6.2. Cache Memory; 6.3. SummaryExercises; References and Further Reading; 7. Memory System Design II; 7.1. Main Memory; 7.2. Virtual Memory; 7.3. Read-Only Memory; 7.4. Summary; Exercises; References and Further Reading; 8. Input-Output Design and Organization; 8.1. Basic Concepts; 8.2. Programmed I/O; 8.3. Interrupt-Driven I/O; 8.4. Direct Memory Access (DMA); 8.5. Buses; 8.6. Input-Output Interfaces; 8.7. Summary; Exercises; References and Further Reading; 9 Pipelining Design Techniques; 9.1. General Concepts; 9.2. Instruction Pipeline; 9.3. Example Pipeline Processors; 9.4. Instruction-Level Parallelism; 9.5. Arithmetic Pipeline9.6. Summary; Exercises; References and Further Reading; 10 Reduced Instruction Set Computers (RISCs); 10.1. RISC/CISC Evolution Cycle; 10.2. RISCs Design Principles; 10.3. Overlapped Register Windows; 10.4. RISCs Versus CISCs; 10.5. Pioneer (University) RISC Machines; 10.6. Example of Advanced RISC Machines; 10.7. Summary; Exercises; References and Further Reading; 11 Introduction to Multiprocessors; 11.1. Introduction; 11.2. Classification of Computer Architectures; 11.3. SIMD Schemes; 11.4. MIMD Schemes; 11.5. Interconnection Networks; 11.6. Analysis and Performance Metrics11.7. Summary; Exercises; References and Further Reading; Index
• Sommario/riassunto: This is the first book in the two-volume set offering comprehensive coverage of the field of computer organization and architecture. This book provides complete coverage of the subjects pertaining to introductory courses in computer organization and architecture, including:* Instruction set architecture and design* Assembly language programming* Computer arithmetic* Processing unit design* Memory system design* Input-output design and organization* Pipelining design techniques* Reduced Instruction Set Computers (RISCs)The authors, who share over 15 years of