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Record Nr. |
UNINA9910813763203321 |
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Autore |
Voldman Steven H |
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Titolo |
ESD : design and synthesis / / Steven H. Voldman |
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Pubbl/distr/stampa |
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Chichester, West Sussex, U.K., : Wiley, 2011 |
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ISBN |
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9786613405272 |
9781283405270 |
128340527X |
9781119991144 |
1119991145 |
9781119991137 |
1119991137 |
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Edizione |
[1st edition] |
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Descrizione fisica |
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1 online resource (292 p.) |
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Collana |
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Classificazione |
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Disciplina |
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Soggetti |
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Semiconductors - Protection |
Integrated circuits - Protection |
Electrostatics |
Analog electronic systems - Design and construction |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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ESD Design and Synthesis; Contents; About the Author; Preface; Acknowledgments; 1 ESD Design Synthesis; 1.1 ESD DESIGN SYNTHESIS AND ARCHITECTURE FLOW; 1.1.1 Top-Down ESD Design; 1.1.2 Bottom-Up ESD Design; 1.1.3 Top-Down ESD Design - Memory Semiconductor Chips; 1.1.4 Top-Down ESD Design - ASIC Design System; 1.2 ESD DESIGN - THE SIGNAL PATH AND THE ALTERNATE CURRENT PATH; 1.3 ESD ELECTRICAL CIRCUIT AND SCHEMATIC ARCHITECTURE CONCEPTS; 1.3.1 The Ideal ESD Network and the Current-Voltage DC Design Window; 1.3.2 The ESD Design Window |
1.3.3 The Ideal ESD Networks in the Frequency Domain Design Window1.4 MAPPING SEMICONDUCTOR CHIPS AND ESD DESIGNS; 1.4.1 Mapping Across Semiconductor Fabricators; 1.4.2 ESD Design Mapping Across Technology Generations; 1.4.3 Mapping from Bipolar Technology to CMOS Technology; 1.4.4 Mapping from Digital CMOS |
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Technology to Mixed Signal Analog-Digital CMOS Technology; 1.4.5 Mapping from Bulk CMOS Technology to Silicon on Insulator (SOI); 1.4.6 ESD Design - Mapping CMOS to RF CMOS Technology; 1.5 ESD CHIP ARCHITECTURE, AND ESD TEST STANDARDS; 1.5.1 ESD Chip Architecture and ESD Testing |
1.6 ESD TESTING1.6.1 ESD Qualification Testing; 1.6.2 ESD Test Models; 1.6.3 ESD Characterization Testing; 1.6.4 TLP Testing; 1.7 ESD CHIP ARCHITECTURE AND ESD ALTERNATIVE CURRENT PATHS; 1.7.1 ESD Circuits, I/O, and Cores; 1.7.2 ESD Signal Pin Circuits; 1.7.3 ESD Power Clamp Networks; 1.7.4 ESD Rail-to-Rail Circuits; 1.7.5 ESD Design and Noise; 1.7.6 Internal Signal Path ESD Networks; 1.7.7 Cross-Domain ESD Networks; 1.8 ESD NETWORKS, SEQUENCING, AND CHIP ARCHITECTURE; 1.9 ESD DESIGN SYNTHESIS - LATCHUP-FREE ESD NETWORKS; 1.10 ESD DESIGN CONCEPTS - BUFFERING - INTER-DEVICE |
1.11 ESD DESIGN CONCEPTS - BALLASTING - INTER-DEVICE1.12 ESD DESIGN CONCEPTS - BALLASTING - INTRA-DEVICE; 1.13 ESD DESIGN CONCEPTS - DISTRIBUTED LOAD TECHNIQUES; 1.14 ESD DESIGN CONCEPTS - DUMMY CIRCUITS; 1.15 ESD DESIGN CONCEPTS - POWER SUPPLY DE-COUPLING; 1.16 ESD DESIGN CONCEPTS - FEEDBACK LOOP DE-COUPLING; 1.17 ESD LAYOUT AND FLOORPLAN-RELATED CONCEPTS; 1.17.1 Design Symmetry; 1.17.2 Design Segmentation; 1.17.3 ESD Design Concepts - Utilization of Empty Space; 1.17.4 ESD Design Synthesis - Across Chip Line Width Variation (ACLV); 1.17.5 ESD Design Concepts - Dummy Shapes |
1.17.6 ESD Design Concepts - Dummy Masks1.17.7 ESD Design Concepts - Adjacency; 1.18 ESD DESIGN CONCEPTS - ANALOG CIRCUIT TECHNIQUES; 1.19 ESD DESIGN CONCEPTS - WIRE BONDS; 1.20 DESIGN RULES; 1.20.1 ESD Design Rule Checking (DRC); 1.20.2 ESD Layout vs. Schematic (LVS); 1.20.3 Electrical Resistance Checking (ERC); 1.21 SUMMARY AND CLOSING COMMENTS; PROBLEMS; REFERENCES; 2 ESD Architecture and Floorplanning; 2.1 ESD DESIGN FLOORPLAN; 2.2 PERIPHERAL I/O DESIGN; 2.2.1 Pad-Limited Peripheral I/O Design Architecture; 2.2.2 Pad-Limited Peripheral I/O Design Architecture - Staggered I/O |
2.2.3 Core-Limited Peripheral I/O Design Architecture |
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Sommario/riassunto |
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Electrostatic discharge (ESD) continues to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a whole-chip ESD design synthesis approach. It provides a clear insight into the integration of ESD protection networks from a generalist perspective, followed by examples in specific technologies, circuits, and chips. Uniquely both the semiconductor chip integration issues and floorplanning of ESD networks are covered from a 'top-down' design approach. Look inside for extensive coverage |
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