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1. |
Record Nr. |
UNINA9910792789303321 |
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Autore |
Taxidis Ilias |
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Titolo |
Les Épigrammes de Maxime Planude : Introduction, édition critique, traduction française et annotation / / Ilias Taxidis |
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Pubbl/distr/stampa |
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Berlin ; ; Boston : , : De Gruyter, , [2017] |
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©2017 |
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ISBN |
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Descrizione fisica |
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1 online resource (XVI, 192 p.) |
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Collana |
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Byzantinisches Archiv ; ; 32 |
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Disciplina |
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Soggetti |
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Byzantine literature - History and criticism - Criticism, interpretation, etc |
Byzantine literature - History and criticism |
Byzantium |
Epigramm |
Maximus Planudes |
epigrams |
palaeologan renaissance |
HISTORY / Medieval |
Criticism, interpretation, etc. |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di contenuto |
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Frontmatter -- Avant-Propos -- Table de matières -- Abréviations -- Bibliographie -- Introduction -- Les Épigrammes -- Index |
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Sommario/riassunto |
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This annotated critical edition presents the epigrams of the Byzantine scholar Maximus Planudes. Due to the absence of a critical edition of almost all Maximus Planudes’ epigrams as well as of a methodical commentary or a systematic review of their thematic, lexical, stylistic and metrical features, this study aims to elucidate the least recognised facet of the literary work of one of the most important scholar of the Palaiologan Renaissance. |
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2. |
Record Nr. |
UNISA996574994103316 |
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Titolo |
1500-2022 - IEEE Standard Testability Method for Embedded Core-based Integrated Circuits / / IEEE |
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Pubbl/distr/stampa |
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New York : , : IEEE, , 2022 |
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ISBN |
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Descrizione fisica |
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1 online resource (168 pages) |
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Disciplina |
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Soggetti |
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Integrated circuits - Testing |
Embedded computer systems - Testing |
Systems on a chip - Testing - Standards |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Sommario/riassunto |
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A mechanism for the test of core designs within a system on chip (SoC) is defined. This mechanism is a hardware architecture and the core test language (CTL) is leveraged to facilitate communication between core designers and core integrators. |
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