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Record Nr. |
UNINA9910785095503321 |
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Titolo |
System-on-chip test architectures [[electronic resource] ] : nanometer design for testability / / edited by Laung-Terng Wang, Charles E. Stroud, Nur A. Touba |
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Pubbl/distr/stampa |
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Amsterdam ; ; Boston, : Morgan Kaufmann Publishers, c2008 |
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ISBN |
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1-281-10004-8 |
9786611100049 |
0-08-055680-9 |
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Descrizione fisica |
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1 online resource (893 p.) |
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Collana |
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The Morgan Kaufmann series in systems on silicon |
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Altri autori (Persone) |
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WangLaung-Terng |
StroudCharles E |
ToubaNur A |
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Disciplina |
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Soggetti |
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Systems on a chip - Testing |
Integrated circuits - Very large scale integration - Testing |
Integrated circuits - Very large scale integration - Design |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Front Cover; System-on-Chip Test Architectures; Copyright Page; Table of Contents; Preface; In the Classroom; Acknowledgments; Contributors; About the Editors; Chapter 1 Introduction; 1.1 Importance of System-on-Chip Testing; 1.1.1 Yield and Reject Rate; 1.1.2 Reliability and System Availability; 1.2 Basics of SOC Testing; 1.2.1 Boundary Scan (IEEE 1149.1 Standard); 1.2.2 Boundary Scan Extension (IEEE 1149.6 Standard); 1.2.3 Boundary-Scan Accessible Embedded Instruments (IEEE P1687); 1.2.4 Core-Based Testing (IEEE 1500 Standard); 1.2.5 Analog Boundary Scan (IEEE 1149.4 Standard) |
1.3 Basics of Memory Testing1.4 SOC Design Examples; 1.4.1 BioMEMS Sensor; 1.4.2 Network-on-Chip Processor; 1.5 About This Book; 1.5.1 DFT Architectures; 1.5.2 New Fault Models and Advanced Techniques; 1.5.3 Yield and Reliability Enhancement; 1.5.4 Nanotechnology Testing Aspects; 1.6 Exercises; Acknowledgments; References; Chapter 2 Digital Test Architectures; 2.1 Introduction; 2.2 Scan Design; 2.2.1 Scan Architectures; 2.2.1.1 Muxed-D Scan Design; 2.2.1.2 Clocked-Scan |
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