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Record Nr. |
UNINA9910782299303321 |
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Autore |
Goldman Stanley J. |
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Titolo |
Phase-locked loop engineering handbook for integrated circuits / / Stanley Goldman |
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Pubbl/distr/stampa |
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Boston : , : Artech House, , ©2007 |
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[Piscataqay, New Jersey] : , : IEEE Xplore, , [2007] |
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ISBN |
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Descrizione fisica |
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1 online resource (572 p.) |
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Collana |
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Artech House microwave library |
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Disciplina |
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Soggetti |
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Integrated circuits - Design and construction |
Phase-locked loops |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Phase-Locked Loop Engineering Handbook for Integrated Circuits; Contents vii; Preface xiii; Acknowledgments xxi; Chapter 1 Getting Started with PLLs 1; Chapter 2 System Analysis 15; Chapter 3 System Requirements 35; Chapter 4 Components, Part 1-Dividers and Oscillators 163; Chapter 5 Components, Part 2-Detectors and Other Circuits 235; Chapter 6 Loop-Compensation Synthesis Revisited 307; Chapter 7 Test and Measurement 353; Chapater 8 Simulation 405; Chapter 9 Applications and Extensions 445; Appendix A Letter Symbols 529; Appendix B Glossary 533; About the Author 541; Index 543 |
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Sommario/riassunto |
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Phased-locked loops (PLLs) are control systems that have become indispensable in today's electronic circuitry. This highly accessible handbook is an practical resource that electronics engineers and circuit designers will find invaluable when developing these systems. PLLs are highly complex to design and are just as difficult to test. To speed development and ensure effective testing, engineers can turn to this collection of practical solutions, SPICE listings, simulation techniques, and testing set-ups. The book offers in-depth coverage of monolithic phase-locked loops and the latest generat. |
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