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Record Nr. |
UNINA9910777912103321 |
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Titolo |
Practical design verification / / edited by Dhiraj K. Pradhan, Ian G. Harris [[electronic resource]] |
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Pubbl/distr/stampa |
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Cambridge : , : Cambridge University Press, , 2009 |
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ISBN |
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1-107-19643-4 |
1-282-39124-0 |
0-511-64683-6 |
9786612391248 |
0-511-62691-6 |
0-511-57932-2 |
0-511-65091-4 |
0-511-57858-X |
0-511-58006-1 |
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Descrizione fisica |
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1 online resource (xi, 276 pages) : digital, PDF file(s) |
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Disciplina |
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Soggetti |
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Integrated circuits - Verification |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Title from publisher's bibliographic system (viewed on 05 Oct 2015). |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Model checking and equivalence checking / Masahiro Fujita -- Transaction-level system modeling / Daniel Gajski and Samar Abdi -- Response checkers, monitors, and assertions / Harry Foster -- System debugging strategies / Wayne H. Wolf -- Test generation and coverage metrics / Ernesto Sánchez, Giovanni Squillero, and Matteo Sonza Reorda -- SystemVerilog and Vera in a verification flow / Shireesh Verma and Ian G. Harris -- Decision diagrams for verification / Maciej Ciesielski, Dhiraj K. Pradhan, and Abusaleh M. Jabir -- Boolean satisfiability and EDA applications / Joao Marques-Silva. |
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Sommario/riassunto |
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Improve design efficiency and reduce costs with this practical guide to formal and simulation-based functional verification. Giving you a theoretical and practical understanding of the key issues involved, expert authors including Wayne Wolf and Dan Gajski explain both formal techniques (model checking, equivalence checking) and |
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simulation-based techniques (coverage metrics, test generation). You get insights into practical issues including hardware verification languages (HVLs) and system-level debugging. The foundations of formal and simulation-based techniques are covered too, as are more recent research advances including transaction-level modeling and assertion-based verification, plus the theoretical underpinnings of verification, including the use of decision diagrams and Boolean satisfiability (SAT). |
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