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Record Nr. |
UNINA9910736029603321 |
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Autore |
Han Donghyeon |
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Titolo |
On-Chip Training NPU - Algorithm, Architecture and SoC Design [[electronic resource] /] / by Donghyeon Han, Hoi-Jun Yoo |
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Pubbl/distr/stampa |
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Cham : , : Springer Nature Switzerland : , : Imprint : Springer, , 2023 |
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ISBN |
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Edizione |
[1st ed. 2023.] |
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Descrizione fisica |
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1 online resource (249 pages) |
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Altri autori (Persone) |
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Disciplina |
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Soggetti |
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Electronic circuits |
Embedded computer systems |
Microprocessors |
Computer architecture |
Electronic Circuits and Systems |
Embedded Systems |
Processor Architectures |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di contenuto |
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Chapter 1 Introduction -- Chapter 2 A Theoretical Study on Artificial Intelligence Training -- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer -- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network -- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning -- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching -- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation -- Chapter 8 An Overview of Energy-efficient DNN Training Processors -- Chapter 9 Conclusion. |
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Sommario/riassunto |
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Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device |
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DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding. Focuses on the requirements and challenges of on-device deep neural network (DNN) training, rather than DNN inference; Provides guidelines for on-device, DNN training semiconductor or System-on-Chip (SoC) design; Includes on-device training semiconductors and SoC design examples to facilitate understanding. |
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