1.

Record Nr.

UNINA9910713345003321

Titolo

Evaluation of a M-151 Jeep and two 1973 Ford Capris powered by 141 CID PROCO stratified charge engines

Pubbl/distr/stampa

[Ann Arbor, Mich.] : , : Environmental Protection Agency, Office of Mobile Source Air Pollution Control, Emission Control Technology Division, Technology Assessment and Evaluation Branch, , 1975

Descrizione fisica

1 online resource (24 pages, 13 unnumbered pages) : illustrations

Soggetti

Stratified charge engines

Lingua di pubblicazione

Inglese

Formato

Materiale a stampa

Livello bibliografico

Monografia

Note generali

"June 1975."

"75-27 GRS."

Nota di bibliografia

Includes bibliographical references.

2.

Record Nr.

UNINA9910437921603321

Titolo

UTLEON3 : exploring fine-grain multi-threading in FPGAs / / Martin Danek ... [et al.]

Pubbl/distr/stampa

New York, : Springer, 2013

ISBN

1-283-74045-1

1-4614-2410-0

Descrizione fisica

1 online resource (228 p.)

Altri autori (Persone)

DanekMartin

Disciplina

621.395

Soggetti

Threads (Computer programs)

Field programmable gate arrays

Lingua di pubblicazione

Inglese

Formato

Materiale a stampa

Livello bibliografico

Monografia

Note generali

Description based upon print version of record.

Nota di bibliografia

Includes bibliographical references and index.

Nota di contenuto

pt. 1. Programming interface -- pt. 2. Implementation.



Sommario/riassunto

This book describes a specification, microarchitecture, VHDL implementation and evaluation of a SPARC v8 CPU with fine-grain multi-threading, called micro-threading. The CPU, named UTLEON3, is an alternative platform for exploring CPU multi-threading that is compatible with the industry-standard GRLIB package. The processor microarchitecture was designed to map in an efficient way the data-flow scheme on a classical von Neumann pipelined processing used in common processors, while retaining full binary compatibility with existing legacy programs.  Describes and documents a working SPARC v8, with fine-grain multithreading and fast context switch; Provides VHDL sources for the described processor; Describes a latency-tolerant framework for coupling hardware accelerators to microthreaded processor pipelines; Includes programming by example in the micro-threaded assembly language.    .