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Record Nr. |
UNINA9910633915603321 |
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Autore |
Bairamkulov Rassul |
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Titolo |
Graphs in VLSI / / Rassul Bairamkulov, Eby G. Friedman |
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Pubbl/distr/stampa |
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Cham, Switzerland : , : Springer, , 2023 |
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©2023 |
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ISBN |
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Descrizione fisica |
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1 online resource (356 pages) |
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Soggetti |
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Graph theory |
Integrated circuits - Very large scale integration |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Intro -- Preface -- Acknowledgments -- Contents -- About the Authors -- 1 Introduction -- 1.1 Precursors of VLSI -- 1.2 The rise of VLSI -- 1.3 Outline of book -- 2 Graph fundamentals -- 2.1 Graph categories -- 2.1.1 Hypergraph -- 2.1.2 Graphs with parallel edges -- 2.1.3 Graphs without parallel edges -- 2.1.4 Weighted graph -- 2.1.5 Directed graph -- 2.2 Inter-graph relationships -- 2.3 Graph exploration -- 2.4 Bipartite graph -- 2.5 Directed acyclic graph -- 2.6 Tree -- 2.7 Common problems in graph theory -- 2.7.1 Pathfinding -- 2.7.1.1 Depth-first search -- 2.7.1.2 Breadth-first search -- 2.7.1.3 Dijkstra's algorithm -- 2.7.1.4 Bellman-Ford -- 2.7.1.5 A* (A-star) algorithm -- 2.7.2 Spanning tree -- 2.7.2.1 Borůvka's algorithm -- 2.7.2.2 Prim's algorithm -- 2.7.2.3 Kruskal's algorithm -- 2.7.2.4 Advanced MST Algorithms -- 2.7.2.5 Steiner tree -- 2.7.3 Graph coloring -- 2.7.4 Topological sorting -- 2.8 Summary -- 3 Graphs in VLSI circuits and systems -- 3.1 Graphs as a VLSI abstraction tool -- 3.2 Register transfer level -- 3.2.1 Register allocation -- 3.2.2 Task scheduling -- 3.2.3 Synchronization -- 3.3 Gate layer -- 3.3.1 Ordered binary decision diagram -- 3.3.2 And-inverter graph -- 3.4 Circuit layer -- 3.4.1 Laplacian matrix of a circuit graph -- 3.5 Physical layer -- 3.5.1 Partitioning -- 3.5.2 Floorplanning -- 3.5.3 Placement -- 3.5.4 Routing -- 3.6 Summary -- 4 Synchronization in VLSI -- 4.1 Graph-based timing analysis -- 4.1.1 Timing constraints in |
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