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Record Nr. |
UNINA9910555117603321 |
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Autore |
Tripathi Suman Lata |
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Titolo |
Digital VLSI design and simulation with Verilog / / Suman Lata Tripathi [et al.] |
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Pubbl/distr/stampa |
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Hoboken, NJ : , : John Wiley & Sons, Inc., , [2022] |
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©2022 |
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ISBN |
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1-119-77808-5 |
1-119-77809-3 |
1-119-77806-9 |
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Descrizione fisica |
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1 online resource (222 pages) |
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Disciplina |
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Soggetti |
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Integrated circuits - Very large scale integration - Design and construction |
Verilog (Computer hardware description language) |
Electronic books. |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Sommario/riassunto |
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The integrated circuits are now growing its importance in every electronic system that needs an efficient VLSI architecture designs with low power consumption, compress chip area, speed, and operating frequency. The challenge for VLSI system designers is to optimize the hardware-software integration for lowering the total cost of acquisition of products. So, there is a demand for better technological solutions for advanced VLSI architectures that can be done through hardware description language (HDL). Verilog HDL is one of the programming languages that can give better solutions to this new era of the VLSI industry. |
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