Evolutionary and memetic computing for project portfolio selection and scheduling / / Kyle Robert Harrison [and five others] editors

• Record Nr.: UNINA9910523747903321
• Pubbl/distr/stampa: Cham, Switzerland : , : Springer, , [2022]; ©2022
• ISBN: 3-030-88315-9
• Descrizione fisica: 1 online resource (218 pages) : VIII, 214 p. 52 illus., 24 illus. in color
• Collana: Adaptation, Learning and Optimization ; ; Volume 26
• Disciplina: 006.3823
• Soggetti: Evolutionary computation; Computer scheduling
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Nota di contenuto: Intro -- Preface -- Contents -- Evolutionary and Memetic Computing for Project Portfolio Selection and Scheduling: An Introduction -- 1 Introduction -- 2 Problem Formulation -- 3 Solution Methodologies -- 3.1 Mathematical Optimization -- 3.2 Evolutionary Computation -- 3.3 Memetic Computing -- 4 Summary of Chapters -- 5 Guide for Readers -- References -- Evolutionary Approaches for Project Portfolio Optimization: An Overview -- 1 Introduction -- 2 Problem Description -- 2.1 Public and Social Projects -- 2.2 Software/IT Projects -- 2.3 R&amp -- D and Production Projects -- 2.4 Construction and Infrastructure Projects -- 2.5 Investment Projects -- 2.6 Defense Projects -- 2.7 Summary of Problem Descriptions -- 3 Problem Formulation -- 3.1 Basic Problem Formulation -- 3.2 Public and Social Projects -- 3.3 Software/IT Projects -- 3.4 R&amp -- D and Production Projects -- 3.5 Construction and Infrastructure Projects -- 3.6 Investment Projects -- 3.7 Defense Projects -- 3.8 Summary of Formulations -- 4 Solution Approaches -- 4.1 Public and Social Projects -- 4.2 Software/IT Projects -- 4.3 R&amp -- D and Production Projects -- 4.4 Construction and Infrastructure Projects -- 4.5 Investment Projects -- 4.6 Defense Projects -- 4.7 Summary of Solution Approaches -- 5 Summary -- References -- An Introduction to Evolutionary and Memetic Algorithms for Parameter Optimization -- 1 Introduction -- 2 Comparison Between EAs and Classical ; Optimization Methods -- 2.1 Robustness -- 2.2 Efficiency -- 3 Building Blocks of EAs -- 4 Genetic Algorithm -- 4.1 Initialization -- 4.2 Selection -- 4.3 Crossover -- 4.4 Mutation -- 4.5 Population Update -- 4.6 Stopping Criteria -- 5 Evolution Strategies -- 5.1 Selection -- 5.2 Recombination -- 5.3 Mutation -- 5.4 Adjusting the Mutation Profile -- 6 Evolutionary Programming -- 7 Differential Evolution -- 7.1 Mutation.; 7.2 Crossover -- 7.3 Selection -- 7.4 Recent Variants -- 8 Other Relevant Methods -- 9 Memetic Algorithms -- 10 Summary and Conclusions -- References -- An Overall Characterization of the Project Portfolio Optimization Problem and an Approach Based on Evolutionary Algorithms to Address It -- 1 Introduction -- 2 A Review of the Project Portfolio Selection Process -- 2.1 Phases in the Project Portfolio Selection Process -- 2.2 Characterizing a Plausible Project Portfolio Selection Approach -- 3 Problem Statement -- 3.1 Problem Description -- 3.2 An Illustrative Example -- 3.3 Problem Formalization -- 4 An Overall Approach to Project Portfolio Selection -- 4.1 Framework of the Approach -- 4.2 Coping with Imperfect Information on the Criteria Impacts -- 4.3 Representing Preferences -- 4.4 Using Evolutionary Algorithms to Optimize Portfolios -- 5 Conclusions and Future Work -- References -- A New Model for the Project Portfolio Selection and Scheduling Problem with Defence Capability Options -- 1 Introduction -- 2 Background -- 2.1 The Knapsack Problem -- 2.2 Evolutionary Meta-Heuristic Approaches -- 2.3 Differential Evolution -- 3 Problem Formulation -- 3.1 Analysis of Problem Formulation -- 3.2 NP-Hardness -- 3.3 Sample Problem Data -- 3.4 Similarity to Existing Problems -- 4 Heuristic Solution Approach -- 5 Experimental Design -- 5.1 Synthetic Problem Instance Generation -- 5.2 Problem Instances -- 5.3 Algorithmic Control Parameters -- 5.4 Statistical Analysis -- 6 Results -- 6.1 Validating the Solution Approaches -- 6.2 Effect of Seeding -- 6.3 Main Results -- 6.4 Summary -- 7 Conclusions and Future Work -- References -- Analysis of New Approaches Used in Portfolio Optimization: A Systematic Literature Review -- 1 Introduction -- 2 Research Method -- 2.1 Research Questions -- 2.2 Search Sources -- 2.3 Inclusion Criteria and Exclusion Criteria.; 2.4 Data Extraction -- 2.5 Data Analysis -- 2.6 Deviations in the Protocol -- 3 Results -- 3.1 Journal Impact Factor -- 3.2 Classification of Methods -- 4 Discussion -- 4.1 Which Key Methods, Tools, or Optimization Techniques Are Used in the Portfolio Optimization Problem? -- 4.2 Which Realistic Constraints Are Used? -- 4.3 What Type of Analysis Is Done Regarding the Stock: Fundamental, Technical, or Mixed (Fundamental and Technical)? -- 4.4 Which Software/Programming Languages Are Used? -- 4.5 Recent Researches -- 5 Conclusions -- 6 Research Gaps -- References -- A Temporal Knapsack Approach to Defence Portfolio Selection -- 1 Introduction -- 2 Project and Portfolio Selection in DoD -- 3 Problem Formulation -- 3.1 Inherent Solution Challenges -- 4 Implementation in Microsoft Excel® -- 5 Performance and Budget-Value Trade-Offs -- 5.1 Relaxation -- 5.2 Value-Slack Trade-Offs and the Issue of Sensitivity -- 6 Discussion and Future Work -- References -- A Decision Support System for Planning Portfolios of Supply Chain Improvement Projects in the Semiconductor Industry -- 1 Introduction -- 2 Literature -- 3 Decision Making Framework and Integer Programming Model -- 4 Decision Support System -- 5 Case Study -- 6 Conclusions and Future Research -- References -- Index.

Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings / / edited by Nadine Azemard, Lars Svensson

• Record Nr.: UNINA9910484643403321
• Pubbl/distr/stampa: Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2007
• ISBN: 3-540-74442-8
• Edizione: [1st ed. 2007.]
• Descrizione fisica: 1 online resource (XIV, 586 p.)
• Collana: Theoretical Computer Science and General Issues, , 2512-2029 ; ; 4644
• Disciplina: 621.395
• Soggetti: Logic design; Microprocessors; Computer architecture; Electronic digital computers - Evaluation; Computer arithmetic and logic units; Computer storage devices; Memory management (Computer science); Electronic circuits; Logic Design; Processor Architectures; System Performance and Evaluation; Arithmetic and Logic Structures; Computer Memory Structure; Electronic Circuits and Systems
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Includes index.
• Nota di bibliografia: Includes bibliographical references and index.
• Nota di contenuto: Session 1 - High-Level Design (1) -- System-Level Application-Specific NoC Design for Network and Multimedia Applications -- Fast and Accurate Embedded Systems Energy Characterization Using Non-intrusive Measurements -- A Flexible General-Purpose Parallelizing Architecture for Nested Loops in Reconfigurable Platforms -- An Automatic Design Flow for Mapping Application onto a 2D Mesh NoC ; Architecture -- Session 2 - Low Power Design Techniques -- Template Vertical Dictionary-Based Program Compression Scheme on the TTA -- Asynchronous Functional Coupling for Low Power Sensor Network Processors -- A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs -- Low-Power Content Addressable Memory With Read/Write and Matched Mask Ports -- The Design and Implementation of a Power Efficient Embedded SRAM -- Session 3 - Low Power Analog Circuits -- Design of a Linear Power Amplifier with ±1.5V Power Supply Using ALADIN -- Settling Time Minimization of Operational Amplifiers -- Low-Voltage Low-Power Curvature-Corrected Voltage Reference Circuit Using DTMOSTs -- Session 4 - Statistical Static Timing Analysis -- Computation of Joint Timing Yield of Sequential Networks Considering Process Variations -- A Simple Statistical Timing Analysis Flow and Its Application to Timing Margin Evaluation -- A Statistical Approach to the Timing-Yield Optimization of Pipeline Circuits -- Session 5 - Power Modeling and Optimization -- A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect -- Modelling the Impact of High Level Leakage Optimization Techniques on the Delay of RT-Components -- Logic Style Comparison for Ultra Low Power Operation in 65nm Technology -- Design-In Reliability for 90-65nm CMOS Nodes Submitted to Hot-Carriers and NBTI Degradation -- Session 6 - Low Power RoutingOptimization -- Clock Distribution Techniques for Low-EMI Design -- Crosstalk Waveform Modeling Using Wave Fitting -- Weakness Identification for Effective Repair of Power Distribution Network -- New Adaptive Encoding Schemes for Switching Activity Balancing in On-Chip Buses -- On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects -- Session 7 - High Level Design (2) -- Soft Error-Aware Power Optimization Using Gate Sizing -- Automated Instruction Set Characterization and Power Profile Driven Software Optimization for Mobile Devices -- RTL Power Modeling and Estimation of Sleep Transistor Based Power Gating -- Functional Verification of Low Power Designs at RTL -- XEEMU: An Improved XScale Power Simulator -- Session 8 - Security and Asynchronous Design -- Low Power Elliptic Curve Cryptography -- Design and Test of Self-checking Asynchronous Control Circuit -- An Automatic Design Flow for Implementation of Side Channel Attacks Resistant Crypto-Chips -- Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA -- Session 9 - Low Power Applications -- Performance Optimization of Embedded Applications in a Hybrid Reconfigurable Platform -- The Energy Scalability of Wavelet-Based, Scalable Video Decoding -- Direct Memory Access Optimization in Wireless Terminals for Reduced Memory Latency and Energy Consumption -- Poster 1 - Modeling and Optimization -- Exploiting Input Variations for Energy Reduction -- A Model of DPA Syndrome and Its Application to the Identification of Leaking Gates -- Static Power Consumption in CMOS Gates Using Independent Bodies -- Moderate Inversion: Highlights for Low Voltage Design -- On Two-Pronged Power-Aware Voltage Scheduling for Multi-processor Real-Time Systems -- SemiCustom Design: A Case Study on SIMD Shufflers -- Poster 2 - High Level Design -- Optimization for Real-Time Systems with Non-convex Power Versus Speed Models -- Triple-Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS -- A Fast and Accurate Power Estimation Methodology for QDI Asynchronous Circuits -- Subthreshold Leakage Modeling and Estimation of General CMOS Complex Gates -- A Platform for Mixed HW/SW Algorithm Specifications for the Exploration of SW and HW Partitioning -- Fast Calculation of Permissible Slowdown Factors for Hard Real-Time ; Systems -- Design Methodology and Software Tool for Estimation of Multi-level Instruction Cache Memory Miss Rate -- Poster 3 - Low Power Techniques and Applications -- A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations -- Switching Activity Reduction of MAC-Based FIR Filters with Correlated Input Data -- Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply -- Low-Power Digital Filtering Based on the Logarithmic Number System -- A Power Supply Selector for Energy- and Area-Efficient Local Dynamic Voltage Scaling -- Dependability Evaluation of Time-Redundancy Techniques in Integer Multipliers -- Keynotes -- Design and Industrialization Challenges of Memory Dominated SOCs -- Statistical Static Timing Analysis: A New Approach to Deal with Increased Process Variability in Advanced Nanometer Technologies -- Analog Power Modelling -- Industrial Session - Design Challenges in Real-Life Projects -- Technological Trends, Design Constraints and Design Implementation Challenges in Mobile Phone Platforms -- System Design from Instrument Level Down to ASIC Transistors with Speed and Low Power as Driving Parameters.
• Sommario/riassunto: th Welcome to the proceedings of PATMOS 2007, the 17 in a series of international workshops. PATMOS 2007 was organized by Chalmers University of Technology with IEEE Sweden Chapter of the Solid-State Circuit Society technical - sponsorship and IEEE CEDA sponsorship. Over the years, PATMOS has evolved into an important European event, where - searchers from both industry and academia discuss and investigate the emerging ch- lenges in future and contemporary applications, design methodologies, and tools - quired for the development of the upcoming generations of integrated circuits and systems. The technical program of PATMOS 2007 consisted of state-of-the-art te- nical contributions, three invited talks and an industrial session on design challenges in real-life projects. The technical program focused on timing, performance and power consumption, as well as architectural aspects with particular emphasis on m- eling, design, characterization, analysis and optimization in the nanometer era. The Technical Program Committee, with the assistance of additional expert - viewers, selected the 55 papers presented at PATMOS. The papers were organized into 9 technical sessions and 3 poster sessions. As is always the case with the PATMOS workshops, full papers were required, and several reviews were received per manuscript.