| |
|
|
|
|
|
|
|
|
1. |
Record Nr. |
UNINA9910483947603321 |
|
|
Titolo |
Hardware and software, verification and testing : third International Haifa Verification Conference, HVC 2007, Haifa, Israel, October 23-25, 2007 : proceedings / / Karen Yorav (editor) |
|
|
|
|
|
|
|
Pubbl/distr/stampa |
|
|
Berlin, Germany : , : Springer, , [2008] |
|
©2008 |
|
|
|
|
|
|
|
|
|
ISBN |
|
|
|
|
|
|
Edizione |
[1st ed. 2008.] |
|
|
|
|
|
Descrizione fisica |
|
1 online resource (XII, 267 p.) |
|
|
|
|
|
|
Collana |
|
Programming and Software Engineering ; ; 4899 |
|
|
|
|
|
|
Disciplina |
|
|
|
|
|
|
Soggetti |
|
Computer input-output equipment |
Software architecture |
Computer programs - Verification |
|
|
|
|
|
|
|
|
Lingua di pubblicazione |
|
|
|
|
|
|
Formato |
Materiale a stampa |
|
|
|
|
|
Livello bibliografico |
Monografia |
|
|
|
|
|
Note generali |
|
|
|
|
|
|
Nota di bibliografia |
|
Includes bibliographical references and index. |
|
|
|
|
|
|
Nota di contenuto |
|
Invited Talks -- Simulation vs. Formal: Absorb What Is Useful; Reject What Is Useless -- Scaling Commercial Verification to Larger Systems -- From Hardware Verification to Software Verification: Re-use and Re-learn -- Where Do Bugs Come from? -- HVC Award -- Symbolic Execution and Model Checking for Testing -- Hardware Verification -- On the Characterization of Until as a Fixed Point Under Clocked Semantics -- Reactivity in SystemC Transaction-Level Models -- Model Checking -- Verifying Parametrised Hardware Designs Via Counter Automata -- How Fast and Fat Is Your Probabilistic Model Checker? An Experimental Performance Comparison -- Dynamic Hardware Verification -- Constraint Patterns and Search Procedures for CP-Based Random Test Generation -- Using Virtual Coverage to Hit Hard-To-Reach Events -- Merging Formal and Testing -- Test Case Generation for Ultimately Periodic Paths -- Dynamic Testing Via Automata Learning -- Formal Verification for Software -- On the Architecture of System Verification Environments -- Exploiting Shared Structure in Software Verification Conditions -- Delayed Nondeterminism in Model Checking Embedded Systems Assembly Code -- A Complete Bounded Model Checking Algorithm for Pushdown Systems -- Software Testing -- Locating Regression Bugs -- The Advantages of Post-Link Code |
|
|
|
|
|
|
|
|
|
|
|
Coverage -- GenUTest: A Unit Test and Mock Aspect Generation Tool. |
|
|
|
|
|
|
Sommario/riassunto |
|
This book constitutes the thoroughly refereed post-workshop proceedings of the Third International Haifa Verification Conference, HVC 2007, held in Haifa, Israel, in October 2007. The 15 revised full papers presented together with 4 invited lectures were carefully reviewed and selected from 32 submissions. The papers are organized in topical tracks on hardware verification, model checking, dynamic hardware verification, merging formal and testing, formal verification for software and software testing. |
|
|
|
|
|
|
|
| |