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1. |
Record Nr. |
UNINA9910452453403321 |
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Titolo |
Guide to the diagnosis of work-related musculoskeletal disorders . Volume 1 Carpal tunnel syndrome [[electronic resource] /] / Louis Patry ... [et al.] |
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Pubbl/distr/stampa |
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Sainte-Foy, Québec, : Éditions MultiMondes, c1998 |
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ISBN |
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2-89544-219-3 |
1-4356-2587-0 |
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Descrizione fisica |
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1 online resource (48 p.) |
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Altri autori (Persone) |
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Disciplina |
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Soggetti |
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Carpal tunnel syndrome - Diagnosis |
Overuse injuries - Diagnosis |
Musculoskeletal system - Wounds and injuries - Diagnosis |
Industrial accidents |
Electronic books. |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references. |
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Nota di contenuto |
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""First Cover""; ""PREFACE""; ""INTRODUCTION""; ""TABLE OF CONTENTS""; ""List of Figures""; ""List of Tables""; ""List of Boxes""; ""Chapter 1 � General Considerations""; ""Terminology""; ""Epidemiology""; ""Anatomical Review""; ""Pathophysiology""; ""Chapter 2 � Etiology""; ""Pathologies that Modify the Shape of the Carpal Tunnelor Increase the Volume of its Contents""; ""Systemic Pathologies and Specific Conditions""; ""Work-Relatedness of Musculoskeletal Strain""; ""Compression of the Median Nerve in the Carpal Tunnel""; ""Compression of the Thenar Branch of the Median Nerve"" |
""Chapter 3 � Differential Diagnosis""""Disorders of the Central Nervous System""; ""Disorders of the Peripheral Nervous System""; ""Chapter 4 � Clinical Considerations""; ""Symptoms""; ""Location of Symptoms (Where?)""; ""Onset of Symptoms (When?)""; ""Characteristics of Onset (How?) ""; ""Impact on Activities of Daily Living""; ""Chapter 5 � Recording of Information on Exposure Factors""; ""Occupational History""; ""Previous Work""; ""Current Work""; ""Current Work and Organisational Factors""; ""Sports-related, Recreational, and Household |
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Activities"" |
""Chapter 6 � Clinical Examination""""Observation and Palpation""; ""Provocative Tests""; ""Evaluation of Sensitivity""; ""Strength Testing""; ""Electrophysiologic Tests""; ""Chapter 7 � Summary of the Evaluation""; ""Chapter 8 � Guidelines for Therapeutic and Preventive Interventions""; ""Therapeutic Guidelines""; ""Prevention Guidelines""; ""Conclusion""; ""Bibliography""; ""Back Cover"" |
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2. |
Record Nr. |
UNINA9910780944203321 |
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Autore |
Yiu Joseph |
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Titolo |
The definitive guide to the ARM Cortex-M3 [[electronic resource] /] / Joseph Yiu |
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Pubbl/distr/stampa |
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Amsterdam ; ; Boston, : Newnes, c2010 |
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ISBN |
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1-282-75584-6 |
9786612755842 |
1-85617-964-8 |
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Edizione |
[2nd ed.] |
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Descrizione fisica |
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1 online resource (481 p.) |
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Disciplina |
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Soggetti |
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Embedded computer systems |
Microprocessors |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Front Cover; Half Title Page; The Definitive Guide to the ARM Cortex-M3; Copyright Page; Table of Contents; Foreword; Foreword; Preface; Acknowledgments; Conventions; Terms and Abbreviations; Chapter 1. Introduction; 1.1 What Is the ARM Cortex-M3 Processor?; 1.2 Background of ARM and ARM Architecture; 1.2.1 A Brief History; 1.2.2 Architecture Versions; 1.2.3 Processor Naming; 1.3 Instruction Set Development; 1.4 The Thumb-2 Technology and Instruction Set Architecture; 1.5 Cortex-M3 Processor Applications; 1.6 Organization of This Book; 1.7 Further Reading; Chapter 2. Overview of the Cortex-M3 |
2.1 Fundamentals2.2 Registers; 2.2.1 R0-R12: General-Purpose Registers; 2.2.2 R13: Stack Pointers; 2.2.3 R14: The Link Register; 2.2.4 R15: The Program Counter; 2.2.5 Special Registers; 2.3 Operation |
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Modes; 2.4 The Built-In Nested Vectored Interrupt Controller; 2.4.1 Nested Interrupt Support; 2.4.2 Vectored Interrupt Support; 2.4.3 Dynamic Priority Changes Support; 2.4.4 Reduction of Interrupt Latency; 2.4.5 Interrupt Masking; 2.5 The Memory Map; 2.6 The Bus Interface; 2.7 The MPU; 2.8 The Instruction Set; 2.9 Interrupts and Exceptions; 2.9.1 Low Power and High Energy Efficiency |
2.10 Debugging Support2.11 Characteristics Summary; 2.11.1 High Performance; 2.11.2 Advanced Interrupt-Handling Features; 2.11.3 Low Power Consumption; 2.11.4 System Features; 2.11.5 Debug Supports; Chapter 3. Cortex-M3 Basics; 3.1 Registers; 3.1.1 General Purpose Registers R0 through R7; 3.1.2 General Purpose Registers R8 through R12; 3.1.3 Stack Pointer R13; 3.1.4 Link Register R14; 3.1.5 Program Counter R15; 3.2 Special Registers; 3.2.1 Program Status Registers; 3.2.2 PRIMASK, FAULTMASK, and BASEPRI Registers; 3.2.3 The Control Register; 3.3 Operation Mode; 3.4 Exceptions and Interrupts |
3.5 Vector Tables3.6 Stack Memory Operations; 3.6.1 Basic Operations of the Stack; 3.6.2 Cortex-M3 Stack Implementation; 3.6.3 The Two-Stack Model in the Cortex-M3; 3.7 Reset Sequence; Chapter 4. Instruction Sets; 4.1 Assembly Basics; 4.1.1 Assembler Language: Basic Syntax; 4.1.2 Assembler Language: Use of Suffixes; 4.1.3 Assembler Language: Unified Assembler Language; 4.2 Instruction List; 4.2.1 Unsupported Instructions; 4.3 Instruction Descriptions; 4.3.1 Assembler Language: Moving Data; 4.3.2 LDR and ADR Pseudo-Instructions; 4.3.3 Assembler Language: Processing Data |
4.3.4 Assembler Language: Call and Unconditional Branch4.3.5 Assembler Language: Decisions and Conditional Branches; 4.3.6 Assembler Language: Combined Compare and Conditional Branch; 4.3.7 Assembler Language: Instruction Barrier and Memory Barrier Instructions; 4.3.8 Assembly Language: Saturation Operations; 4.4 Several Useful Instructions in the Cortex-M3; 4.4.1 MSR and MRS; 4.4.2 More on the IF-THEN Instruction Block; 4.4.3 SDIV and UDIV; 4.4.4 REV, REVH, and REVSH; 4.4.5 Reverse Bit; 4.4.6 SXTB, SXTH, UXTB, and UXTH; 4.4.7 Bit Field Clear and Bit Field Insert; 4.4.8 UBFX and SBFX |
4.4.9 LDRD and STRD |
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Sommario/riassunto |
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This user's guide does far more than simply outline the ARM Cortex-M3 CPU features; it explains step-by-step how to program and implement the processor in real-world designs. It teaches readers how to utilize the complete and thumb instruction sets in order to obtain the best functionality, efficiency, and reuseability. The author, an ARM engineer who helped develop the core, provides many examples and diagrams that aid understanding. Quick reference appendices make locating specific details a snap! Whole chapters are dedicated to: Debugging using the new CoreSight technologyMi |
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