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Record Nr. |
UNINA9910437913103321 |
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Autore |
Czerwinski Robert |
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Titolo |
Finite state machine logic synthesis for complex programmable logic devices / / Robert Czerwinski and Dariusz Kania |
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Pubbl/distr/stampa |
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New York, : Springer, 2013 |
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ISBN |
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Edizione |
[1st ed. 2013.] |
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Descrizione fisica |
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1 online resource (xiv, 172 pages) : illustrations |
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Collana |
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Lecture notes in electrical engineering, , 1876-1100 ; ; 231 |
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Altri autori (Persone) |
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Disciplina |
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Soggetti |
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Signal processing - Digital techniques |
Algorithms |
Computer architecture |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Introduction -- Definitions and Basic Properties -- Synthesis of FSMs -- State Assignment Algorithms -- Theoretical Background of Technology-Dependent Optimization -- The Algorithm of Area Optimization Based on Graphs of Outputs -- Conclusions -- Output File Format -- Conclusion. |
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Sommario/riassunto |
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This book is a monograph devoted to logic synthesis and optimization for CPLDs. CPLDs' macrocell can also be interpreted as programmable AND-fixed OR structure, well known as PAL-based structure. The question is: what should be done when the number of implicants representing function exceeds the number of product terms available in a logic block. The answer is ... in the book. Logic synthesis and optimization methods dedicated for PAL-based structures are proposed. The methods strive to find the optimum fit for the combinational logic and finite state machines to the structure of the logic device and aim at area and speed optimization. The theoretical background and complete strategies are richly illustrated with examples and figures. |
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