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1. |
Record Nr. |
UNINA9910312140003321 |
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Autore |
Stati Uniti d'America. Bureau of the Census |
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Titolo |
Central America / Bureau of the Census ; in cooperation with Foreign Operation Administration |
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Pubbl/distr/stampa |
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Washington : U.S. Department of Commerce, 1955 |
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Descrizione fisica |
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10 carte geografiche ripieg., 4 p. : in cartella ; 29 cm |
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Collana |
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Census atlas maps of latin America |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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2. |
Record Nr. |
UNINA9910407735903321 |
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Autore |
Taraate Vaibbhav |
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Titolo |
SystemVerilog for Hardware Description : RTL Design and Verification / / by Vaibbhav Taraate |
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Pubbl/distr/stampa |
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Singapore : , : Springer Singapore : , : Imprint : Springer, , 2020 |
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ISBN |
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Edizione |
[1st ed. 2020.] |
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Descrizione fisica |
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1 online resource (258 pages) |
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Disciplina |
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Soggetti |
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Electronic circuits |
Microprogramming |
Electronics |
Microelectronics |
Circuits and Systems |
Control Structures and Microprogramming |
Electronics and Microelectronics, Instrumentation |
Electronic Circuits and Devices |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di contenuto |
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Chapter 1: Introduction to FPGA design -- Chapter 2: Introduction to HDL -- Chapter 3:Introduction to SystemVerilog -- Chapter 4: Programming using SystemVerilog -- Chapter 5:Combinational design using SystemVerilog -- Chapter 6: Sequential design using SystemVerilog -- Chapter 7: RTL design using SystemVerilog -- Chapter 8: Verification using SystemVerilog -- Chapter 9: Design Implementation using FPGA. |
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Sommario/riassunto |
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This book introduces the reader to FPGA based design for RTL synthesis. It describes simple to complex RTL design scenarios using SystemVerilog. The book builds the story from basic fundamentals of FPGA based designs to advance RTL design and verification concepts using SystemVerilog. It provides practical information on the issues in the RTL design and verification and how to overcome these. It focuses on writing efficient RTL codes using SystemVerilog, covers design for the Xilinx FPGAs and also includes implementable code examples. The contents of this book cover improvement of design performance, assertion based verification, verification planning, and architecture and system testing using FPGAs. The book can be used for classroom teaching or as a supplement in lab work for undergraduate and graduate coursework as well as for professional development and training programs. It will also be of interest to researchers and professionals interested in the RTL design for FPGA and ASIC. |
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