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1. |
Record Nr. |
UNISA990003365640203316 |
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Autore |
VERDESCA, Daniele |
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Titolo |
Il registro di cantiere per la sicurezza : guida all'utilizzo, liste di controllo, modulistica completa / Daniele Verdesca |
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Pubbl/distr/stampa |
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Santarcangelo di Romagna : Maggioli, 2010 |
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ISBN |
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Edizione |
[3. ed. aggiornata con le modifiche introdotte dal d.lgs 106/2009 al Testo unico sulla sicurezza] |
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Descrizione fisica |
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312 p. ; 30 cm + 1 Cd-Rom |
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Collana |
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Sicurezza & cantiere ; 168 |
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Disciplina |
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Soggetti |
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Cantieri edili - Sicurezza |
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Collocazione |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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2. |
Record Nr. |
UNINA9910366590703321 |
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Autore |
Chakravarthi Veena S |
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Titolo |
A Practical Approach to VLSI System on Chip (SoC) Design : A Comprehensive Guide / / by Veena S. Chakravarthi |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2020 |
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ISBN |
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Edizione |
[1st ed. 2020.] |
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Descrizione fisica |
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1 online resource (XXXII, 312 p. 204 illus.) |
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Disciplina |
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Soggetti |
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Electronic circuits |
Microtechnology |
Microelectromechanical systems |
Computer engineering |
Computer networks |
Microprocessors |
Computer architecture |
Electronic Circuits and Systems |
Microsystems and MEMS |
Computer Engineering and Networks |
Processor Architectures |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di contenuto |
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Introduction -- SoC design methodology -- System on Chip Components -- DFT and Synthesis -- Static timing Analysis (STA) -- VLSI System Verification -- Physical Design -- Advanced Techniques: Low power UPF flow -- Reference Design: Specification to Layout. |
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Sommario/riassunto |
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This book provides a comprehensive overview of the VLSI design process. It covers end-to-end system on chip (SoC) design, including design methodology, the design environment, tools, choice of design components, handoff procedures, and design infrastructure needs. The book also offers critical guidance on the latest UPF-based low power design flow issues for deep submicron SOC designs, which will prepare |
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readers for the challenges of working at the nanotechnology scale. This practical guide will provide engineers who aspire to be VLSI designers with the techniques and tools of the trade, and will also be a valuable professional reference for those already working in VLSI design and verification with a focus on complex SoC designs. A comprehensive practical guide for VLSI designers; Covers end-to-end VLSI SoC design flow; Includes source code, case studies, and application examples. |
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