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Record Nr. |
UNINA9910349358003321 |
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Titolo |
62142-2005 - IEC/IEEE iInternational standard - Verilog(R) Register Transfer Level synthesis / / Institute of Electrical and Electronics Engineers |
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Pubbl/distr/stampa |
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New York, New York : , : IEEE, , 2002 |
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ISBN |
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Descrizione fisica |
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1 online resource (116 pages) |
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Disciplina |
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Soggetti |
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VHDL (Computer hardware description language) |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Sommario/riassunto |
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Replaces IEEE Std 1364.1-2002. To develop a standard syntax and semantics for Verilog RTL synthesis. This standard shall define the subset of IEEE 1364 (Verilog HDL) which is suitable for RTL synthesis and shall define the semantics of that subset for the synthesis domain. This standard shall be based on the current existing standard IEEE 1364. |
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