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1. |
Record Nr. |
UNINA9910557534403321 |
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Autore |
Kronvang Brian |
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Titolo |
Land Use and Water Quality |
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Pubbl/distr/stampa |
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Basel, Switzerland, : MDPI - Multidisciplinary Digital Publishing Institute, 2020 |
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Descrizione fisica |
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1 online resource (248 p.) |
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Soggetti |
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Environmental economics |
Research and information: general |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Sommario/riassunto |
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This collection of 11 papers introduces broad topics covering various professional disciplines related to the research arena of land use and water quality. The papers exemplify the important links between agriculture and water quality in surface and ground waters as well as the pollution problems around urban areas. Advancement of new technologies for analyzing links between land use and water quality problems as well as insights into new tools for analyzing large monitoring datasets are highlighted in this collection of papers. |
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2. |
Record Nr. |
UNINA9910337645003321 |
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Autore |
Lee Weng Fook |
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Titolo |
Learning from VLSI Design Experience / / by Weng Fook Lee |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2019 |
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ISBN |
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Edizione |
[1st ed. 2019.] |
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Descrizione fisica |
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1 online resource (xxix, 214 pages) |
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Disciplina |
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Soggetti |
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Electronic circuits |
Microprocessors |
Electronics |
Microelectronics |
Circuits and Systems |
Processor Architectures |
Electronics and Microelectronics, Instrumentation |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di contenuto |
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Chapter 1. Introduction -- Chapter 2. Design Methodology and Flow -- Chapter 3. Multiple Clock Design -- Chapter 4. Latch Inference -- Chapter 5. Design for Test -- Chapter 6. Signed Verilog -- Chapter 7. State Machine -- Chapter 8. RTL Coding Guideline -- Chapter 9. Code Coverage. . |
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Sommario/riassunto |
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This book shares with readers practical design knowledge gained from the author’s 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their |
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workarounds. Addresses practical design issues and their workarounds; Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine; Provides readers with an RTL coding guideline, based on real experience. |
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