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Record Nr. |
UNINA9910337620903321 |
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Autore |
Taraate Vaibbhav |
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Titolo |
Advanced HDL Synthesis and SOC Prototyping : RTL Design Using Verilog / / by Vaibbhav Taraate |
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Pubbl/distr/stampa |
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Singapore : , : Springer Singapore : , : Imprint : Springer, , 2019 |
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ISBN |
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Edizione |
[1st ed. 2019.] |
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Descrizione fisica |
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1 online resource (xxi, 307 pages) |
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Disciplina |
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Soggetti |
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Electronic circuits |
Microprogramming |
Logic design |
Circuits and Systems |
Control Structures and Microprogramming |
Logic Design |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Nota di contenuto |
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Introduction -- SOC Design -- RTL Design Guidelines -- RTL Design and Verification -- Processor cores and Architecture design -- Buses and protocols in SOC designs -- DSP Algorithms and Video Processing -- ASIC and FPGA Synthesis -- Static Timing Analysis -- SOC Prototyping -- SOC Prototyping guidelines -- Design Integration and SOC synthesis -- Interconnect delays and Timing -- SOC Prototyping and debug techniques -- Testing at the board level. |
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Sommario/riassunto |
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This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using modern high density Field Programmable Gate Arrays (FPGAs) is discussed in this book with the practical examples and case studies. The book discusses SOC design, performance improvement techniques, testing and system level verification, while also describing the modern Intel FPGA/XILINX FPGA architectures and their use in SOC prototyping. Further, the book covers the Synopsys Design Compiler (DC) and Prime |
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Time (PT) commands, and how they can be used to optimize complex ASIC/SOC designs. The contents of this book will be useful to students and professionals alike. |
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