Governance of Indian state power utilities : an ongoing journey / / Sheoli Pargal and Kristy Mayer

• Record Nr.: UNINA9910787147703321
• Autore: Pargal Sheoli
• Pubbl/distr/stampa: Washington, DC : , : World Bank, , [2014]
• ISBN: 1-4648-0304-8
• Descrizione fisica: 1 online resource (xviii, 111 pages) : illustrations ; ; 24 cm
• Collana: India power sector review
• Disciplina: 354.4/90954
• Soggetti: Electric utilities - India; Public utilities - India
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Description based upon print version of record.
• Nota di bibliografia: Includes bibliographical references at the end of each chapters.
• Nota di contenuto: Front Cover; Contents; Acknowledgments; About the Authors; Executive Summary; Abbreviations; Chapter 1 Introduction; Notes; References; Chapter 2 Institutional Context; Figures; Figure 2.1 Timeline-Establishment of SERCs; Figure 2.2 Timeline of Power Sector Unbundling (Orange) and Central Electricity Acts and Policies (Green); Notes; References; Chapter 3 Corporate Governance of State Power Utilities; Boxes; Box 3.1 Literature on Corporate Governance; Objectives of Unbundling and Corporatizing State Utilities; Figure 3.1 Power Sector Structures, 2010; Corporate Governance Requirements for State Utilities in India Findings-Corporate Governance in Practice; Box 3.2 Types of Directors; Box 3.3 Shunglu Committee Recommendations on Corporate and Regulatory Governance; Figure 3.2 Utilities with More than Two Government Directors; Figure 3.3 Government Involvement in Different Utility Decisions; Figure 3.4 Utilities with Board Share of Independent Directors Meeting DPE Guidelines; Figure 3.5 Utilities That Have a Dedicated Regulatory Cell; Figure 3.6 Utilities That File Their Accounts on Time and Make Accounts and Audit Reports Public; Figure 3.7 Average Chairperson/Managing Director Tenure Figure 3.8 Number of Directors on Utility Boards; Figure 3.9 Average Number of Board Meetings per Year; Figure 3.10 Utilities with Audit Committees; Figure 3.11 Utilities with an Independent Director Chairing the Audit Committee; Figure 3.12 Utilities with Executive Directors Constituting ; Less or More than Half of Board Members; Figure 3.13 Utilities with an ERP System or Advanced MIS; Tables; Table 3.1 Share of Utilities in Compliance with Indicators That Constitute the Basic Index; Box 3.4 Corporate Governance as an Instrument of Change in West Bengal Table 3.2 Characteristics of the Top Five Utilities Covered in the Detailed Index; Box 3.5 Corporate Governance in a High Performing Joint Venture-Tata Power (Delhi); Box 3.6 Organizational Transformation and a Turnaround in Performance in Gujarat; Table 3.3 Utility Performance on the Detailed Index; Notes; Table 3.4 Correlation among Corporate Governance (CG) Variables; References; Chapter 4 Regulatory Governance; Mandates of SERCs; Implementation of Regulatory Mandates; Box 4.1 SERC Responsibilities; Figure 4.1 Ratio of Average Billed Tariff to Operating-Cost-Recovery Level and to Average Operating Cost, 2010 Figure 4.2 Change in Ratio of Average Billed Tariff to Operating-Cost-Recovery Level, 2003-10; Box 4.2 The Cost of Regulatory Assets; Figure 4.3 Measures Taken by SERCs to Protect Consumer Rights; Figure 4.4 Number of Regulations Notified by SERCs; Figure 4.5 Types of Regulations Notified by SERCs; Figure 4.6 Action Taken on OA by SERCs; Institutional Design: SERC Autonomy, Capacity, Transparency, and Accountability; Figure 4.7 Action Taken on Renewable Energy and Energy Efficiency by SERCs
• Sommario/riassunto: This World Bank review, Governance of Indian State Power Utilities: An Ongoing Journey, is a first attempt to systematically examine the quality of corporate and regulatory governance in the Indian power sector. Considering that much of the poor performance of utilities reflected internal and external shortfalls in governance, India's Electricity Act of 2003 mandated unbundling and corporatizing the vertically integrated state electricity boards, along with establishing independent regulators at the center and in the states. The aim was to create a more accountable and commercial performance c

Logic synthesis for finite state machines based on linear chains of states : foundations, recent developments and challenges / / by Alexander Barkalov, Larysa Titarenko, Jacek Bieganowski

• Record Nr.: UNINA9910299908703321
• Autore: Barkalov Alexander
• Pubbl/distr/stampa: Cham : , : Springer International Publishing : , : Imprint : Springer, , 2018
• ISBN: 3-319-59837-6
• Edizione: [1st ed. 2018.]
• Descrizione fisica: 1 online resource (VIII, 225 p. 145 illus.)
• Collana: Studies in Systems, Decision and Control, , 2198-4182 ; ; 113
• Disciplina: 511.3
• Soggetti: Computational intelligence; Electronic circuits; Computational Intelligence; Circuits and Systems
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Nota di bibliografia: Includes bibliographical references at the end of each chapters and index.
• Nota di contenuto: Introduction -- Finite state machines and field-programmable gate arrays -- Linear chains in FSMs -- Hardware reduction for Moore UFSMs -- Hardware reduction for Mealy UFSMs -- Hardware reduction for Moore NFSMs -- Hardware reduction for Moore XFSMs.
• Sommario/riassunto: This book discusses Moore finite state machines (FSMs) implemented with field programmable gate arrays (FPGAs) including look-up table (LUT) elements and embedded memory blocks (EMBs). To minimize the number of LUTs in FSM logic circuits, the authors propose replacing a state register with a state counter. They also put forward an approach allowing linear chains of states to be created, which simplifies the system of input memory functions and, therefore, decreases the number of LUTs in the resulting FSM circuit. The authors combine this approach with using EMBs to implement the system of output functions (microoperations). This allows a significant decrease in the number of LUTs, as well as eliminating a lot of interconnections in the FSM logic circuit. As a rule, it also reduces the area occupied by the circuit and diminishes the resulting power dissipation. This book is an interesting and valuable resource for students and postgraduates in the area of ; computer science, as well as for designers of digital systems that included complex control units.