1.

Record Nr.

UNINA9910299860203321

Autore

Zhao Feng

Titolo

Low-Noise Low-Power Design for Phase-Locked Loops : Multi-Phase High-Performance Oscillators / / by Feng Zhao, Fa Foster Dai

Pubbl/distr/stampa

Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015

ISBN

3-319-12200-2

Edizione

[1st ed. 2015.]

Descrizione fisica

1 online resource (106 p.)

Disciplina

620

621.381

621.3815

621.382

Soggetti

Electronic circuits

Electronics

Microelectronics

Signal processing

Image processing

Speech processing systems

Circuits and Systems

Electronics and Microelectronics, Instrumentation

Signal, Image and Speech Processing

Lingua di pubblicazione

Inglese

Formato

Materiale a stampa

Livello bibliografico

Monografia

Note generali

Description based upon print version of record.

Nota di contenuto

Introduction -- Analysis of Quantization Noise Reduction Techniques for Fractional-N PLL -- A Wide-Band 0.13µm SiGe BiCMOS PLL for X-Band Radar -- Design and Analysis of QVCO with Different Coupling Techniques -- Design and Analysis of a 0.6V QVCO with Capacitive-Coupling Technique -- Conclusions.

Sommario/riassunto

This book introduces low-noise and low-power design techniques for phase-locked loops and their building blocks. It summarizes the noise reduction techniques for fractional-N PLL design and introduces a novel capacitive-quadrature coupling technique for multi-phase signal generation.  The capacitive-coupling technique has been validated



through silicon implementation and can provide low phase-noise and accurate I-Q phase matching, with low power consumption from a super low supply voltage.  Readers will be enabled to pick one of the most suitable QVCO circuit structures for their own designs, without additional effort to look for the optimal circuit structure and device parameters. .