1.

Record Nr.

UNINA9910299855103321

Autore

Qu Shichun

Titolo

Wafer-Level Chip-Scale Packaging : Analog and Power Semiconductor Applications / / by Shichun Qu, Yong Liu

Pubbl/distr/stampa

New York, NY : , : Springer New York : , : Imprint : Springer, , 2015

ISBN

1-4939-1556-8

Edizione

[1st ed. 2015.]

Descrizione fisica

1 online resource (336 p.)

Disciplina

620

621.381

621.3815

621.4021

Soggetti

Electronics

Microelectronics

Electronic circuits

Thermodynamics

Heat engineering

Heat transfer

Mass transfer

Electronics and Microelectronics, Instrumentation

Circuits and Systems

Engineering Thermodynamics, Heat and Mass Transfer

Lingua di pubblicazione

Inglese

Formato

Materiale a stampa

Livello bibliografico

Monografia

Note generali

Description based upon print version of record.

Nota di bibliografia

Includes bibliographical references and index.

Nota di contenuto

Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging -- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package -- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package -- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design -- Chapter 5. Wafer Level Discrete Power MOSFET Package Design -- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution -- Chapter 7. Thermal Management, Design, Analysis for WLCSP -- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP -- Chapter 9. WLCSP Typical Assembly Process -- Chapter 10. WLCSP Typical Reliability and Test.



Sommario/riassunto

This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: ·         Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology ·         Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology ·         Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs.