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Record Nr. |
UNINA9910299759203321 |
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Autore |
Meyer-Baese Uwe |
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Titolo |
Digital Signal Processing with Field Programmable Gate Arrays / / by Uwe Meyer-Baese |
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Pubbl/distr/stampa |
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Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2014 |
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ISBN |
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Edizione |
[4th ed. 2014.] |
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Descrizione fisica |
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1 online resource (XXIII, 930 p. 459 illus., 11 illus. in color.) |
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Collana |
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Signals and Communication Technology, , 1860-4862 |
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Disciplina |
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Soggetti |
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Signal processing |
Image processing |
Speech processing systems |
Microprogramming |
Electronic circuits |
Signal, Image and Speech Processing |
Control Structures and Microprogramming |
Circuits and Systems |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di contenuto |
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Computer Arithmetic -- Finite Impulse Response (FIR) Digital Filtres -- Infinite Impulse Response (IIR) Digital Filtres -- Multirate Signal Processing -- Fourier Transforms -- Advanced Topics -- Adaptive Filtres -- Microprocessor Design. |
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Sommario/riassunto |
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Field-Programmable Gate Arrays (FPGAs) are revolutionizing digital signal processing. The efficient implementation of front-end digital signal processing algorithms is the main goal of this book. It starts with an overview of today's FPGA technology, devices, and tools for designing state-of-the-art DSP systems. A case study in the first chapter is the basis for more than 40 design examples throughout. The following chapters deal with computer arithmetic concepts, theory and the implementation of FIR and IIR filters, multirate digital signal processing systems, DFT and FFT algorithms, advanced algorithms with high future potential, and adaptive filters. Each chapter contains exercises. The VERILOG source code and a glossary are given in the |
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appendices. This new edition incorporates Over 10 new system level case studies designed in VHDL and Verilog A new chapter on image and video processing An Altera Quartus update and new ModelSim simulations Xilinx Atlys board and ISIM simulation support Signed fixed point and floating point IEEE library examples An overview on parallel all-pass IIR filter design ICA and PCA system level designs • Speech and audio coding for MP3 and ADPCM. |
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