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Record Nr. |
UNINA9910299666903321 |
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Autore |
Raiteri Daniele |
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Titolo |
Circuit Design on Plastic Foils / / by Daniele Raiteri, Eugenio Cantatore, Arthur van Roermund |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 |
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ISBN |
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Edizione |
[1st ed. 2015.] |
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Descrizione fisica |
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1 online resource (138 p.) |
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Collana |
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Analog Circuits and Signal Processing, , 1872-082X |
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Disciplina |
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Soggetti |
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Electronic circuits |
Electronics |
Microelectronics |
Circuits and Systems |
Electronic Circuits and Devices |
Electronics and Microelectronics, Instrumentation |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references. |
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Nota di contenuto |
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Introduction -- Applications of large-area electronics on foils -- State of the art in circuit design -- Device modeling and characterization -- Sensor frontend architecture -- Circuit design for analog signal conditioning -- Circuit design for data conversion -- Circuit design for digital processing -- Conclusions. |
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Sommario/riassunto |
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This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics. The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing. • Discusses implications of problems associated with large-area electronics and compares them to standard silicon; • Provides the basis for understanding physics and modeling of |
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disordered material; • Includes guidelines to quickly setup the basic CAD tools enabling efficient and reliable designs; • Illustrates practical solutions to cope with hard/soft faults, variability, mismatch, aging and bias stress at architecture, circuit, layout, and device levels. |
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