1.

Record Nr.

UNINA9910299666903321

Autore

Raiteri Daniele

Titolo

Circuit Design on Plastic Foils / / by Daniele Raiteri, Eugenio Cantatore, Arthur van Roermund

Pubbl/distr/stampa

Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015

ISBN

3-319-11427-1

Edizione

[1st ed. 2015.]

Descrizione fisica

1 online resource (138 p.)

Collana

Analog Circuits and Signal Processing, , 1872-082X

Disciplina

620

621.381

621.3815

Soggetti

Electronic circuits

Electronics

Microelectronics

Circuits and Systems

Electronic Circuits and Devices

Electronics and Microelectronics, Instrumentation

Lingua di pubblicazione

Inglese

Formato

Materiale a stampa

Livello bibliografico

Monografia

Note generali

Description based upon print version of record.

Nota di bibliografia

Includes bibliographical references.

Nota di contenuto

Introduction -- Applications of large-area electronics on foils -- State of the art in circuit design -- Device modeling and characterization -- Sensor frontend architecture -- Circuit design for analog signal conditioning -- Circuit design for data conversion -- Circuit design for digital processing -- Conclusions.

Sommario/riassunto

This book illustrates a variety of circuit designs on plastic foils and provides all the information needed to undertake successful designs in large-area electronics.  The authors demonstrate architectural, circuit, layout, and device solutions and explain the reasons and the creative process behind each. Readers will learn how to keep under control large-area technologies and achieve robust, reliable circuit designs that can face the challenges imposed by low-cost low-temperature high-throughput manufacturing.   • Discusses implications of problems associated with large-area electronics and compares them to standard silicon; • Provides the basis for understanding physics and modeling of



disordered material; • Includes guidelines to quickly setup the basic CAD tools enabling efficient and reliable designs; • Illustrates practical solutions to cope with hard/soft faults, variability, mismatch, aging and bias stress at architecture, circuit, layout, and device levels.