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Record Nr. |
UNINA9910299495603321 |
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Autore |
Brandonisio Francesco |
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Titolo |
Noise-shaping all-digital phase-locked loops : modeling, simulation, analysis and design / / Francesco Brandonisio, Michael Peter Kennedy |
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Pubbl/distr/stampa |
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Cham, Switzerland : , : Springer, , 2014 |
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ISBN |
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Edizione |
[1st ed. 2014.] |
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Descrizione fisica |
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1 online resource (xiii, 177 pages) : illustrations (some color) |
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Collana |
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Analog Circuits and Signal Processing, , 1872-082X |
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Disciplina |
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Soggetti |
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Phase-locked loops |
Electronic digital computers - Circuits - Design and construction |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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"ISSN: 1872-082X." |
"ISSN: 2197-1854 (electronic)." |
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Nota di bibliografia |
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Includes bibliographical references at the end of each chapters and index. |
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Nota di contenuto |
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Introduction -- Phase Digitization in All-Digital PLLs -- A Unifying Framework for TDC Architectures -- Analytical Predictions of Phase Noise in ADPLLs -- Advantages of Noise Shaping and Dither -- Efficient Modeling and Simulation of Accumulator-Based ADPLLs -- Modelling and Estimating Phase Noise with Matlab. |
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Sommario/riassunto |
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This book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Readers will gain a deep understanding of ADPLLs and the central role played by noise-shaping. A range of ADPLL and TDC architectures are presented in unified manner. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book. • Discusses in detail a wide range of all-digital phase-locked loops architectures; • Presents a unified framework in which to model time-to-digital converters for ADPLLs; • Explains a procedure to predict and simulate phase noise in oscillators and ADPLLs; • Describes an efficient approach to model |
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