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1. |
Record Nr. |
UNINA990007007150403321 |
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Autore |
Gentili, Alberico |
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Titolo |
Alberici Gentilis iurisconsulti, professoris regii, In titulos codicis si quis imperatori maledixerit, ad legem Iuliam maiestatis, Disputationes decem quarum elenchum auersa pagina ostendit |
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Pubbl/distr/stampa |
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Hanoviae : apud Guilielmum Antonium, 1607 |
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Descrizione fisica |
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Disciplina |
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Locazione |
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Collocazione |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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2. |
Record Nr. |
UNINA9910299494903321 |
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Autore |
Kritikakou Angeliki |
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Titolo |
Scalable and Near-Optimal Design Space Exploration for Embedded Systems / / by Angeliki Kritikakou, Francky Catthoor, Costas Goutis |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2014 |
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ISBN |
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Edizione |
[1st ed. 2014.] |
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Descrizione fisica |
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1 online resource (287 p.) |
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Disciplina |
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004.1 |
006.2/2 |
620 |
621.042 |
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Soggetti |
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Electronic circuits |
Microprocessors |
Electronics |
Microelectronics |
Energy |
Circuits and Systems |
Processor Architectures |
Electronics and Microelectronics, Instrumentation |
Energy, general |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Introduction & Motivation -- Reusable DSE methodology for scalable & near-optimal frameworks -- Part I Background memory management methodologies -- Development of intra-signal in-place methodology -- Pattern representation -- Intra-signal in-place methodology for non-overlapping scenario -- Intra-signal in-place methodology for overlapping scenario -- Part II Processing related mapping methodologies -- Design-time scheduling techniques DSE framework -- Methodology to develop design-time scheduling techniques under constraints -- Design Exploration Methodology for Microprocessor & HW accelerators -- Conclusions & Future Directions. |
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Sommario/riassunto |
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This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies. The authors present design methodologies for data storage and processing in real-time, cost-sensitive data-dominated embedded systems. Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design. • Describes design space exploration (DSE) methodologies for data storage and processing in embedded systems, which achieve near-optimal solutions with scalable exploration time; • Presents a set of principles and the processes which support the development of the proposed scalable and near-optimal methodologies; • Enables readers to apply scalable and near-optimal methodologies to the intra-signal in-place optimization step for both regular and irregular memory accesses. |
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