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1. |
Record Nr. |
UNIBAS000028047 |
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Titolo |
Introduzione alle colture cellulari / Gian Luigi Mariottini ... [et al.] |
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Pubbl/distr/stampa |
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Milano : Tecniche nuove, 2010 |
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ISBN |
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Edizione |
[2. ed] |
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Descrizione fisica |
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IX, 133 p. : ill. ; 24 cm. |
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Altri autori (Persone) |
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Disciplina |
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Soggetti |
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Cellula - Coltura |
Tessuti (istologia) |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Sulla copertina: I libri di Laboratorio 2000 |
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2. |
Record Nr. |
UNICASRML0258778 |
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Titolo |
Lex : abbonamento 2001 (4 cd rom) |
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Pubbl/distr/stampa |
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Soggetti |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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3. |
Record Nr. |
UNINA9910299477603321 |
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Autore |
Mandal Ayan |
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Titolo |
Source-synchronous networks-on-chip : circuit and architectural interconnect modeling / / Ayan Mandal, Sunil P. Khatri, Rabi Mahapatra |
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Pubbl/distr/stampa |
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New York : , : Springer, , 2014 |
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ISBN |
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Edizione |
[1st ed. 2014.] |
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Descrizione fisica |
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1 online resource (xiii, 143 pages) : illustrations (some color) |
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Collana |
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Disciplina |
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004.1 |
620 |
621.381 |
621.3815 |
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Soggetti |
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Networks on a chip - Design |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Introduction -- Clock Distribution for fast Networks-on-Chip -- Fast Network-on-Chip Design -- Fast On-Chip Data transfer using Sinusoid Signals -- Conclusion and Future Work. |
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Sommario/riassunto |
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This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using |
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the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. • Describes novel methods for high-speed network-on-chip (NoC) design; • Enables readers to understand NoC design from both circuit and architectural levels; • Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC; • Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art. |
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