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Record Nr. |
UNINA9910299255103321 |
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Titolo |
VLSI-SoC: Internet of Things Foundations : 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, Playa del Carmen, Mexico, October 6-8, 2014, Revised Selected Papers / / edited by Luc Claesen, Maria-Teresa Sanz-Pascual, Ricardo Reis, Arturo Sarmiento-Reyes |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2015 |
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ISBN |
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Edizione |
[1st ed. 2015.] |
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Descrizione fisica |
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1 online resource (XIV, 241 p. 150 illus. in color.) |
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Collana |
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IFIP Advances in Information and Communication Technology, , 1868-4238 ; ; 464 |
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Disciplina |
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Soggetti |
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Computer organization |
Computer hardware |
Computer-aided engineering |
Computer Systems Organization and Communication Networks |
Computer Hardware |
Computer-Aided Engineering (CAD, CAE) and Design |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Nota di contenuto |
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Intro -- Preface -- Organization -- Contents -- Dynamic Programming-Based Lifetime Reliability Optimization in Networks-on-Chip -- 1 Introduction -- 2 Related Work -- 3 Lifetime Budget Definition -- 4 Lifetime-Aware Adaptive Routing -- 4.1 Problem Definition -- 4.2 Dynamic Programming-Based Formulation -- 4.3 Lifetime-Aware Adaptive Routing Algorithm -- 4.4 Dynamic Programming Network -- 4.5 Lifetime Budget Runtime Computation -- 5 Experimental Results -- 5.1 Experimental Setup -- 5.2 MTTF Distribution -- 5.3 Minimal MTTF Evaluation -- 5.4 NoC Overall MTTF Evaluation -- 5.5 Variance of MTTF -- 5.6 Average Packets Delay Comparison -- 5.7 Hardware Evaluation -- 6 Conclusions and Future Work -- References -- Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs -- Abstract -- 1 Introduction -- 2 Related Work -- 3 Sequential Linear Decompression -- 4 Proposed Architecture -- 5 |
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Optimizing Number of Test Elevators by Inter-layer Serialization of Test Data -- 6 Experimental Results -- 7 Conclusion and Future Work -- References -- Design and Optimization of Multiple-Mesh Clock Network -- 1 Introduction -- 2 Preliminaries -- 2.1 Clock Mesh Structure and Its Synthesis -- 2.2 Multi-level Clock Gating -- 3 Mesh Clock Networks for Multi-level Clock Gating -- 3.1 Single-Mesh Implementation -- 3.2 Multiple-Mesh Implementation -- 3.3 Assessment -- 4 Choosing Mesh Implementation Style -- 4.1 Switching Capacitance Estimation -- 5 Floorplanning of Multiple Meshes -- 5.1 Assessment -- 6 Comparison with Clock Tree -- 6.1 Clock Skew Variation -- 7 Related Work -- 8 Conclusion -- References -- Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture -- 1 Introduction -- 2 Background -- 2.1 STT-RAM Technology -- 2.2 Hybrid Approach for Last-Level Caches -- 2.3 Cache Partitioning Technique -- 3 Partitioning Technique for Hybrid Caches. |
3.1 Motivation -- 3.2 Architecture -- 3.3 Replacement Policy -- 3.4 Allocation Switching Technique -- 4 Evaluation Methodology -- 4.1 Simulator -- 4.2 Workloads -- 5 Results -- 5.1 Performance -- 5.2 Miss Rates -- 5.3 Cache Energy Consumption -- 5.4 DRAM Energy Consumption -- 5.5 Area Overhead -- 6 Related Work -- 6.1 Reducing Write Overhead of STT-RAM -- 6.2 Cache Partitioning for Energy Saving -- 7 Conclusion -- References -- Interval Arithmetic and Self Similarity Based Subthreshold Leakage Optimization in RTL Datapaths -- 1 Introduction and Motivation -- 2 Background, Related Work, and Terminology -- 2.1 Input Vector Control Techniques -- 2.2 Fractals and Self Similarity -- 2.3 Interval Arithmetic -- 2.4 Notation and Problem Formulation -- 3 Self Similarity Based Monte Carlo Characterization for Low Leakage Intervals -- 3.1 Leakage Profile and Scope for Optimization -- 3.2 Self Similarity of Leakage Distributions in n Bit Adders and Multipliers -- 3.3 Monte Carlo Based Low Leakage Interval Search -- 4 Proposed Approach -- 4.1 Motivating Examples -- 4.2 Low Leakage Vector Determination -- 5 Experimental Results -- 6 Conclusion -- References -- 8T-SRAM Cell with Improved Read and Write Margins in 65 nm CMOS Technology -- Abstract -- 1 Introduction -- 2 The Proposed 8T-SRAM Cell -- 3 Simulation Results and Comparison -- 4 Conclusions -- References -- On the Co-simulation of SystemC with QEMU and OVP Virtual Platforms -- 1 Introduction -- 2 Background and Related Works -- 2.1 QEMU -- 2.2 OVP -- 3 Co-simulation Architecture -- 3.1 SystemC Bridge -- 3.2 Virtual Device -- 3.3 Interrupt Handling -- 4 Experimental Results -- 5 Conclusions -- References -- Statistical Evaluation of Digital Techniques for ADC BIST -- 1 Introduction -- 2 Dynamic Test of ADCs Using Digital Ternary Stimuli -- 2.1 Ternary Stimulus: Theoretical Basis. |
2.2 Ternary Stimulus Optimization -- 2.3 Response Evaluation: Theoretical Basis -- 3 Efficient On-chip Implementation -- 4 Simulation Framework -- 5 Case Study -- 5.1 Behavioral Model -- 5.2 Fault-Free Case -- 5.3 Nominal and Extreme Variations -- 5.4 Parametric Test Metrics Estimation -- 6 Conclusion -- References -- A Parallel MCMC-Based MIMO Detector: VLSI Design and Algorithm -- 1 Introduction -- 2 System Model -- 3 MCMC-Based MIMO Detection -- 4 Low-Level Algorithm -- 4.1 Basic Concepts -- 4.2 Overall Algorithm Design -- 4.3 Front-end Processing -- 4.4 Gibbs Sampler -- 4.5 Metric Update -- 4.6 LLR Computation -- 5 VLSI Architecture -- 5.1 Overview -- 5.2 FEP-Circuit -- 5.3 GS/M-Circuit -- 5.4 L-Circuit -- 6 Differences to Reference Architecture -- 7 Results -- 7.1 Simulation Setup -- 7.2 Architecture -- 7.3 Synthesis Results -- 7.4 Layout Results -- 8 Algorithmic Considerations -- 9 Conclusions and Outlook -- References -- Real-Time Omnidirectional Imaging System with |
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Interconnected Network of Cameras -- 1 Introduction -- 2 Omnidirectional Vision Reconstruction Algorithm -- 3 Distributed and Parallel Implementation -- 3.1 Processing Demands -- 3.2 Effects of Pixelation Schemes -- 4 Interconnected Network of Cameras -- 4.1 Camera Assignment Problem -- 4.2 Central Unit Access -- 4.3 Verification -- 5 Panoptic Media Platform -- 5.1 Central FPGA -- 5.2 Slave FPGAs -- 5.3 Inter FPGA Communication -- 5.4 Implementation Results -- 6 Visualization of Omnidirectional Data -- 6.1 Server Application -- 6.2 Client Application -- 6.3 Future Work -- 7 A Real-Time HDR Panorama with Panoptic Camera -- 7.1 HDR Composite Frame -- 7.2 Tone Mapping -- 7.3 FPGA Implementation -- 7.4 Discussion and Future Work -- 8 Conclusion and Future Work -- References -- Transmission Channel Noise Aware Energy Effective LDPC Decoding -- 1 Introduction. |
2 Sum-Product LDPC Decoding -- 3 Proposed Technique -- 3.1 Pre-characterization -- 3.2 Adaptation -- 4 Evaluation -- 5 Conclusions -- References -- Laser-Induced Fault Effects in Security-Dedicated Circuits -- Abstract -- 1 Introduction -- 2 Laser/Silicon Interaction -- 2.1 Photoelectric Effect -- 2.2 Single Event Transient (SET) and Single Event Upset (SEU) -- 3 Global Flow: Overview -- 4 Measures on Bulk and FDSOI Components -- 5 Models: From Physical-Level to Behavioral-Level -- 5.1 Physical-Level -- 5.2 Electrical --Level -- 5.3 Logical Level -- 5.4 Behavioral Level -- 6 CAD Tools -- 7 Counter-Measures -- 7.1 Structure of the Detector -- 7.2 Detector Sensitivity -- 7.3 Insertion of Detectors in the Design -- 8 Conclusions -- Acknowledgment -- References -- Author Index. |
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Sommario/riassunto |
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This book contains extended and revised versions of the best papers presented at the 22nd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2014, held in Playa del Carmen, Mexico, in October 2014. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems. |
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