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1. |
Record Nr. |
UNISA990003363950203316 |
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Autore |
FOUCAULT, Michel |
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Titolo |
Bisogna difendere la società / Michel Foucault ; sotto la direzione di François Ewald e Alessandro Fontana ; a cura di Mauro Bertani e Alessandro Fontana |
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Pubbl/distr/stampa |
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Milano, : Feltrinelli, 2009 |
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ISBN |
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Descrizione fisica |
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Collana |
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Universale economica Feltrinelli , Saggi ; 2089 |
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Disciplina |
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Collocazione |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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2. |
Record Nr. |
UNINA9910254928603321 |
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Titolo |
ICTs in Developing Countries : Research, Practices and Policy Implications / / edited by Bidit Dey, Karim Sorour, Raffaele Filieri |
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Pubbl/distr/stampa |
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London : , : Palgrave Macmillan UK : , : Imprint : Palgrave Macmillan, , 2016 |
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ISBN |
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Edizione |
[1st ed. 2016.] |
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Descrizione fisica |
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1 online resource (212 p.) |
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Disciplina |
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Soggetti |
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International business enterprises |
Development economics |
Business information services |
Telecommunication |
International economic relations |
Strategic planning |
Leadership |
International Business |
Development Economics |
Business Information Systems |
Communications Engineering, Networks |
International Economics |
Business Strategy and Leadership |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Cover; ICTs in Developing Countries; Contents; List of Tables and Figures; Tables; Figures; Preface; Section I Conceptualising digital divide and ICT for development; Section II Dynamics and kinetics of the adoption, use and appropriation of ICTs in developing societies; Section III Policy and practitioner implications; Acknowledgements; Notes on Contributors; Section I: Conceptualising Digital Divide and ICT for Development; 1: A Critical Review of the ICT for Development Research; Introduction; Digital divide: a contentious issue; Narrowing the digital |
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divide: a myth or reality |
Optimistic about bridging the digital divideDoubtful and/or cautiously optimistic; Critical review of some of the ICT-led projects; Theorising ICTs for development; Gap in the current literature and future of ICT4D; Conclusion; Notes; References; 2: Structurational Explication of Technology Adoption in ICT4D : A Throwback to Giddens; Introduction; A return to Giddens' social theory of structuration; Putting the agent back in focus; Duality of structure, agency and knowledgeability, and unintended consequences in structuration; Rules-resources framework |
Power as transformative capacity in structurationICT4D through a Giddensian lens; Modernity and change; The centrality of the 'social'; Concluding remarks; Note; References; Section II: Dynamics and Kinetics of the Adoption, Use and Appropriation of ICTs in Developing Societies; 3: Impacts of Information and Communication Technology Implementation on Regulated Financial Services: The Case of Swaziland; Introduction; Background; Overview of Swaziland and the socio-economic climate; The Swaziland financial system; Methodology; Data collection procedure; Data analysis; Case study |
The direct payroll deduction processExcessive payroll deductions; Implementation of the Central Deduction Administration System (CDAS); Post-implementation impacts and issues; Findings from the case study analysis; Comparison of CDAS versus non-CDAS deductions; Salary advances; Post-implementation compliance issues; Cooperatives - the nature of ownership and stakeholders; Non-complying cooperatives and their impact on the financial market; Lack of government control; Implications; Organizational-level impacts of ICT; Implications for other African nations; Conclusion; Note; Reference |
4: How Young Chinese Consumers Choose among Different Smartphone Brands: The Importance of Socio-cultural and Marketing FactorsIntroduction; Emerging markets and smartphone brands; Methodology; Results; Brand choice influencers; Social influence; Brand popularity; Brand image and loyalty; Design of the smartphone; Mianzi; Smartphone features; Discussion; References; 5: Global Tools Enhance Local Exchange through Community Currency in an Alternate Economy; Introduction; Reciprocal gift e-conomy; The Great Transformation; Relationship economics in a network society; The high-tech gift economy |
Money 2:0 |
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Sommario/riassunto |
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ICTs in Developing Countries is a collection of conceptual and empirical works on the adoption and impacts of ICT use in developing societies. Bringing together a wide range of disciplines and contributors, it offers a rich examination of digital divide and ICT for development both in terms of contextual information and disciplinary perspectives. |
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3. |
Record Nr. |
UNINA9910817124503321 |
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Autore |
Voldman Steven H |
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Titolo |
ESD : failure mechanisms and models / / Steven H. Voldman |
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Pubbl/distr/stampa |
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Chichester, West Sussex, U.K. ; ; Hoboken, NJ, : J. Wiley, 2009 |
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ISBN |
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9786612237133 |
9781282237131 |
1282237136 |
9780470747254 |
0470747250 |
9780470747261 |
0470747269 |
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Edizione |
[1st ed.] |
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Descrizione fisica |
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1 online resource (410 p.) |
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Disciplina |
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Soggetti |
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Semiconductors - Failures |
Integrated circuits - Protection |
Integrated circuits - Testing |
Integrated circuits - Reliability |
Electric discharges |
Electrostatics |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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ESD Failure Mechanisms and Models; Contents; About the Author; Preface; Acknowledgments; 1 Failure Analysis and ESD; 1.1 INTRODUCTION; 1.1.1 FA Techniques for Evaluation of ESD Events; 1.1.2 Fundamental Concepts of ESD FA Methods and Practices; 1.1.3 ESD Failure: Why Do Semiconductor Chips Fail?; 1.1.4 How to Use FA to Design ESD Robust Technologies; 1.1.5 How to Use FA to Design ESD Robust Circuits; 1.1.6 How to Use FA for Temperature Prediction; 1.1.7 How to Use Failure Models for Power Prediction; 1.1.8 FA Methods, Design Rules, and ESD Ground Rules |
1.1.9 FA and Semiconductor Process-Induced ESD Design Asymmetry 1.1.10 FA Methodology and Electro-thermal Simulation; 1.1.11 FA and ESD Testing Methodology; 1.1.12 FA Methodology for Evaluation of ESD |
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Parasitics; 1.1.13 FA Methods and ESD Device Operation Verification; 1.1.14 FA Methodology to Evaluate Inter-power Rail Electrical Connectivity; 1.1.15 How to Use FA to Eliminate Failure Mechanisms; 1.2 ESD FAILURE: HOW DO MICRO-ELECTRONIC DEVICES FAIL?; 1.2.1 ESD Failure: How Do Metallurgical Junctions Fail?; 1.2.2 ESD Failure: How Do Insulators Fail?; 1.2.3 ESD Failure: How Do Metals Fail? |
1.3 SENSITIVITY OF SEMICONDUCTOR COMPONENTS 1.3.1 ESD Sensitivity as a Function of Materials; 1.3.2 ESD Sensitivity as a Function of Semiconductor Devices; 1.3.3 ESD Sensitivity as a Function of Product Type; 1.3.4 ESD and Technology Scaling; 1.3.5 ESD Technology Roadmap; 1.4 HOW DO SEMICONDUCTOR CHIPS FAIL--ARE THE FAILURES RANDOM OR SYSTEMATIC?; 1.5 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 2 Failure Analysis Tools, Models, and Physics of Failure; 2.1 FA TECHNIQUES FOR EVALUATION OF ESD EVENTS; 2.2 FA TOOLS; 2.2.1 Optical Microscope; 2.2.2 Scanning Electron Microscope |
2.2.3 Transmission Electron Microscope 2.2.4 Emission Microscope; 2.2.5 Thermally Induced Voltage Alteration; 2.2.6 Superconducting Quantum Interference Device Microscope; 2.2.7 Atomic Force Microscope; 2.2.8 The 2-D AFM; 2.2.9 Picosecond Current Analysis Tool; 2.2.10 Transmission Line Pulse--Pico second Current Analysis Tool; 2.3 ESD SIMULATION: ESD PULSE MODELS; 2.3.1 Human Body Model; 2.3.2 Machine Model; 2.3.3 Cassette Model; 2.3.4 Socketed Device Model; 2.3.5 Charged Board Model; 2.3.6 Cable Discharge Event; 2.3.7 IEC System-Level Pulse Model; 2.3.8 Human Metal Model |
2.3.9 Transmission Line Pulse Testing 2.3.10 Very Fast Transmission Line Pulse (VF-TLP) Model; 2.3.11 Ultra-fast Transmission Line Pulse (UF-TLP) Model; 2.4 ELECTRO-THERMAL PHYSICAL MODELS; 2.4.1 Tasca Model; 2.4.2 Wunsch-Bell Model; 2.4.3 Smith-Littau Model; 2.4.4 Ash Model; 2.4.5 Arkihpov, Astvatsaturyan, Godovosyn, and Rudenko Model; 2.4.6 Dwyer, Franklin, and Campbell Model; 2.4.7 Vlasov-Sinkevitch Model; 2.5 STATISTICAL MODELS FOR ESD PREDICTION; 2.6 CLOSING COMMENTS AND SUMMARY; PROBLEMS; REFERENCES; 3 CMOS Failure Mechanisms; 3.1 TABLES OF CMOS ESD FAILURE MECHANISMS |
3.2 LOCOS ISOLATION-DEFINED CMOS |
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Sommario/riassunto |
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Electrostatic discharge (ESD) failure mechanisms continue to impact semiconductor components and systems as technologies scale from micro- to nano-electronics. This book studies electrical overstress, ESD, and latchup from a failure analysis and case-study approach. It provides a clear insight into the physics of failure from a generalist perspective, followed by investigation of failure mechanisms in specific technologies, circuits, and systems. The book is unique in covering both the failure mechanism and the practical solutions to fix the problem from either a technology or circuit method |
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