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Record Nr. |
UNINA9910254244803321 |
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Autore |
Zhang Chenxin |
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Titolo |
Heterogeneous Reconfigurable Processors for Real-Time Baseband Processing : From Algorithm to Architecture / / by Chenxin Zhang, Liang Liu, Viktor Öwall |
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Pubbl/distr/stampa |
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Cham : , : Springer International Publishing : , : Imprint : Springer, , 2016 |
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ISBN |
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Edizione |
[1st ed. 2016.] |
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Descrizione fisica |
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1 online resource (203 p.) |
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Disciplina |
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Soggetti |
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Electronic circuits |
Microprocessors |
Electronics |
Microelectronics |
Circuits and Systems |
Processor Architectures |
Electronics and Microelectronics, Instrumentation |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references at the end of each chapters. |
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Nota di contenuto |
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Introduction -- Digital Hardware Platforms -- Digital Baseband Processing -- The Reconfigurable Cell Array -- Multi-standard Digital Front-End Processing -- Multi-task MIMO Signal Processing -- Future Multi-user MIMO systems – A Discussion -- Conclusion.-. |
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Sommario/riassunto |
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This book focuses on domain-specific heterogeneous reconfigurable architectures, demonstrating for readers a computing platform which is flexible enough to support multiple standards, multiple modes, and multiple algorithms. The content is multi-disciplinary, covering areas of wireless communication, computing architecture, and circuit design. The platform described provides real-time processing capability with reasonable implementation cost, achieving balanced trade-offs among flexibility, performance, and hardware costs. The authors discuss efficient design methods for wireless communication processing platforms, from both an algorithm and architecture design perspective. Coverage also includes computing platforms for different wireless |
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technologies and standards, including MIMO, OFDM, Massive MIMO, DVB, WLAN, LTE/LTE-A, and 5G. •Discusses reconfigurable architectures, including hardware building blocks such as processing elements, memory sub-systems, Network-on-Chip (NoC), and dynamic hardware reconfiguration; •Describes a unique design and optimization methodology, applied to different areas and levels, including communication theory, hardware implementation, and software support; •Demonstrates design trade-offs during different development phases and enables readers to apply similar techniques to various applications. |
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