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Record Nr. |
UNINA9910254218503321 |
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Autore |
Taraate Vaibbhav |
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Titolo |
Digital Logic Design Using Verilog : Coding and RTL Synthesis / / by Vaibbhav Taraate |
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Pubbl/distr/stampa |
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New Delhi : , : Springer India : , : Imprint : Springer, , 2016 |
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ISBN |
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Edizione |
[1st ed. 2016.] |
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Descrizione fisica |
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1 online resource (431 p.) |
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Disciplina |
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Soggetti |
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Electronic circuits |
Electronics |
Microelectronics |
Logic design |
Circuits and Systems |
Electronics and Microelectronics, Instrumentation |
Logic Design |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Description based upon print version of record. |
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Nota di bibliografia |
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Includes bibliographical references and index. |
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Nota di contenuto |
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Introduction -- Combinational Logic Design (Part I) -- Combinational Logic Design (Part II) -- Combinational Design Guidelines -- Sequential Logic Design -- Sequential Design Guidelines -- Complex Designs using Verilog RTL -- Finite State Machines -- Simulation Concepts and PLD Based Designs -- RTL Synthesis -- Static Timing Analysis (STA) -- Constraining Design -- Multiple Clock Domain Designs -- Low Power Design -- RTL Design for SOCs. |
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Sommario/riassunto |
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This book is designed to serve as a hands-on professional reference with additional utility as a textbook for upper undergraduate and some graduate courses in digital logic design. This book is organized in such a way that that it can describe a number of RTL design scenarios, from simple to complex. The book constructs the logic design story from the fundamentals of logic design to advanced RTL design concepts. Keeping in view the importance of miniaturization today, the book gives practical information on the issues with ASIC RTL design and how to overcome these concerns. It clearly explains how to write an efficient RTL code and how to improve design performance. The book also |
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