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Record Nr. |
UNINA9910145114803321 |
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Titolo |
2007 European Conference on Circuit Theory and Design |
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Pubbl/distr/stampa |
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[Place of publication not identified], : I E E E, 2007 |
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ISBN |
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1-5090-8649-8 |
1-4244-1342-7 |
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Descrizione fisica |
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Disciplina |
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Soggetti |
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Electric circuits |
Electric filters |
Electric networks |
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Lingua di pubblicazione |
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Formato |
Materiale a stampa |
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Livello bibliografico |
Monografia |
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Note generali |
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Bibliographic Level Mode of Issuance: Monograph |
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Sommario/riassunto |
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3D discrete wavelet transform (DWT) is a compute-intensive task that is usually implemented on specific architectures in many real-time medical imaging systems. In this paper, a novel area-efficient high-throughput 3D DWT architecture is proposed based on distributed arithmetic. A tap-merging technique is used to reduce the size of DA lookup tables. The proposed architectures were designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The synthesis results show the proposed architecture has a low area cost and can run up to 85 MHz, which can perform a five-level 3D wavelet analysis for seven 128 times 128 times 128 volume images per second. |
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