| |
|
|
|
|
|
|
|
|
1. |
Record Nr. |
UNINA9910144431403321 |
|
|
Titolo |
Nano-CMOS design for manufacturabililty [[electronic resource] ] : robust circuit and physical design for sub-65 nm technology nodes / / Ban Wong ... [et al.] |
|
|
|
|
|
|
|
Pubbl/distr/stampa |
|
|
Hoboken, NJ, : Wiley, c2009 |
|
|
|
|
|
|
|
ISBN |
|
1-282-68822-7 |
9786612688225 |
0-470-38282-1 |
1-61583-175-4 |
0-470-38281-3 |
|
|
|
|
|
|
|
|
Descrizione fisica |
|
1 online resource (403 p.) |
|
|
|
|
|
|
Altri autori (Persone) |
|
|
|
|
|
|
Disciplina |
|
|
|
|
|
|
|
|
Soggetti |
|
Metal oxide semiconductors, Complementary - Design and construction |
Integrated circuits - Design and construction |
Nanoelectronics |
Electronic books. |
|
|
|
|
|
|
|
|
Lingua di pubblicazione |
|
|
|
|
|
|
Formato |
Materiale a stampa |
|
|
|
|
|
Livello bibliografico |
Monografia |
|
|
|
|
|
Note generali |
|
Description based upon print version of record. |
|
|
|
|
|
|
Nota di bibliografia |
|
Includes bibliographical references and index. |
|
|
|
|
|
|
Nota di contenuto |
|
NANO-CMOS DESIGN FOR MANUFACTURABILILTY; CONTENTS; PREFACE; ACKNOWLEDGMENTS; 1 Introduction; 1.1 Value of Design for Manufacturability; 1.2 Deficiencies in Boolean-Based Design Rules in the Subwavelength Regime; 1.3 Impact of Variability on Yield and Performance; 1.4 Industry Challenge: The Disappearing Process Window; 1.5 Mobility Enhancement Techniques: A New Source of Variability Induced by Design-Process Interaction; 1.6 Design Dependency of Chip Surface Topology; 1.7 Newly Exacerbated Narrow Width Effect in Nano-CMOS Nodes; 1.8 Well Proximity Effect |
1.9 Need for Model-Based DFM Solutions Beyond 65 nm1.10 Summary; References; I NEWLY EXACERBATED EFFECTS; 2 Lithography-Related Aspects of DFM; 2.1 Economic Motivations for DFM; 2.2 Lithographic Tools and Techniques for Advanced Technology Nodes; 2.2.1 |
|
|
|
|
|
|
|
|
|
|
|
Lithographic Approaches to Sub-90-nm Lithography; 2.2.2 Lithographic Infrastructure; 2.2.3 Immersion Exposure Tools; 2.2.4 Overlay; 2.2.5 Cooptimization of the Mask, the Illuminator, and Apodization; 2.2.6 Optical Proximity Correction; 2.2.7 Double Patterning; 2.2.8 Lithographic Roadmap; 2.3 Lithography Limited Yield |
2.3.1 Deviations of Printed Shape from Drawn Polygon2.3.2 Increased Variabilities; 2.3.3 Catastrophic Failures; 2.4 Lithography-Driven DFM Solutions; 2.4.1 Practical Boundary Conditions for DFM; 2.4.2 Classical Approach; 2.4.3 Printability Checkers; 2.4.4 Model-Based Design Rule Checks; 2.4.5 ASIC Cell Optimizations; 2.4.6 Lithography-Aware Routers; 2.4.7 Advanced OPC Techniques for Improved Manufacturing; References; 3 Interaction of Layout with Transistor Performance and Stress Engineering Techniques; 3.1 Introduction; 3.2 Impact of Stress on Transistor Performance; 3.2.1 Electron Mobility |
3.2.2 Hole Mobility3.2.3 Threshold Voltage; 3.2.4 Junction Leakage; 3.2.5 High Stress Levels; 3.2.6 Crystal Orientations; 3.2.7 Uniaxial, Biaxial, and Arbitrary Stress Patterns; 3.2.8 Stress Gradients; 3.2.9 Effects of Temperature and High Dopant Concentrations; 3.2.10 Stress Effects in Nonsilicon Semiconductors; 3.3 Stress Propagation; 3.3.1 Stress Propagation for Various Stress Source Geometries; 3.3.2 Stress Propagation Through STI and Other Barriers; 3.3.3 Free Boundaries; 3.4 Stress Sources; 3.4.1 Thermal Mismatch: STI and Silicide; 3.4.2 Lattice Mismatch: eSiGe and Si : C |
3.4.3 Layer Growth3.4.4 Intrinsic Stress: CESL and DSL; 3.4.5 Stress Memorization Technique; 3.4.6 Stress Measurement Techniques; 3.4.7 Stress Simulation Techniques; 3.5 Introducing Stress into Transistors; 3.5.1 Stress Evolution During Process Flow; 3.5.2 Stress Relaxation Mechanisms; 3.5.3 Combining Several Stress Sources; 3.5.4 Stress-Engineered Memory Retention; 3.5.5 Layout-Induced Variations; 3.5.6 Bulk Transistors versus SOI and FinFET; References; II DESIGN SOLUTIONS; 4 Signal and Power Integrity; 4.1 Introduction; 4.2 Interconnect Resistance, Capacitance, and Inductance |
4.2.1 Process Scaling and Interconnect Fabrication |
|
|
|
|
|
|
Sommario/riassunto |
|
Discover innovative tools that pave the way from circuit and physical design to fabrication processing Nano-CMOS Design for Manufacturability examines the challenges that design engineers face in the nano-scaled era, such as exacerbated effects and the proven design for manufacturability (DFM) methodology in the midst of increasing variability and design process interactions. In addition to discussing the difficulties brought on by the continued dimensional scaling in conformance with Moore's law, the authors also tackle complex issues in the design process to overcome the difficulties, incl |
|
|
|
|
|
|
|
| |