Iniunccions geuen by the kynges Maiestie [[electronic resource] ] : aswell to the clergie as to the laitie of this realme. Anno. M.D.XLVII

• Record Nr.: UNISA996387547403316
• Autore: Church of England
• Pubbl/distr/stampa: [Imprinted at London, : The laste daie of Iulii, in the first yere of the reigne of our Sovereigne Lord King Edvvard the. VI. by Richard Grafton printer to His Most Royall Maiestie, Anno. 1547]
• Descrizione fisica: [28] p
• Altri autori (Persone): Edward, King of England, <1537-1553.>
• Soggetti: Great Britain Church history 16th century
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Imprint from colophon.; b4r has catchword: 'Testament.' (with stop); c3r last line begins: 'kynge'.; Signatures: a-c⁴ d² .; Formerly STC 10092.; Identified as STC 10092 on UMI microfilm.; Reproduction of the original in the Cambridge University Library.
• Sommario/riassunto: eebo-0021

High Performance Computing -- HiPC 2003 : 10th International Conference, Hyderabad, India, December 17-20, 2003, Proceedings / / edited by Timothy Mark Pinkston, Viktor K. Prasanna

• Record Nr.: UNINA9910144211603321
• Pubbl/distr/stampa: Berlin, Heidelberg : , : Springer Berlin Heidelberg : , : Imprint : Springer, , 2003
• ISBN: 1-280-30655-6; 9786610306558; 3-540-24596-0
• Edizione: [1st ed. 2003.]
• Descrizione fisica: 1 online resource (XX, 512 p.)
• Collana: Lecture Notes in Computer Science, , 0302-9743 ; ; 2913
• Disciplina: 004.1/1
• Soggetti: Microprocessors; Software engineering; Computer organization; Computers; Algorithms; Numerical analysis; Processor Architectures; Software Engineering/Programming and Operating Systems; Computer Systems Organization and Communication Networks; Computation by Abstract Devices; Algorithm Analysis and Problem Complexity; Numeric Computing
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Bibliographic Level Mode of Issuance: Monograph
• Nota di bibliografia: Includes bibliographical references at the end of each chapters and index.
• Nota di contenuto: Keynote Address -- Life’s Duplicities: Sex, Death, and Valis -- Session I – Performance Issues and Power-Aware Architectures -- Performance Analysis of Blue Gene/L Using Parallel Discrete Event Simulation -- An Efficient Web Cache Replacement Policy -- Timing Issues of Operating Mode Switch in High Performance Reconfigurable Architectures -- Power-Aware Adaptive Issue Queue and Register File -- FV-MSB: A ; Scheme for Reducing Transition Activity on Data Buses -- Session II – Parallel/Distributed and Network Algorithms -- A Parallel Iterative Improvement Stable Matching Algorithm -- Self-Stabilizing Distributed Algorithm for Strong Matching in a System Graph -- Parallel Data Cube Construction: Algorithms, Theoretical Analysis, and Experimental Evaluation -- Efficient Algorithm for Embedding Hypergraphs in a Cycle -- Mapping Hypercube Computations onto Partitioned Optical Passive Star Networks -- Keynote Address -- The High Performance Microprocessor in the Year 2013: What Will It Look Like? What It Won’t Look Like? -- Session III – Routing in Wireless, Mobile, and Cut-Through Networks -- FROOTS – Fault Handling in Up*/Down* Routed Networks with Multiple Roots -- Admission Control for DiffServ Based Quality of Service in Cut-Through Networks -- On Shortest Path Routing Schemes for Wireless Ad Hoc Networks -- A Hierarchical Routing Method for Load-Balancing -- Ring Based Routing Schemes for Load Distribution and Throughput Improvement in Multihop Cellular, Ad hoc, and Mesh Networks -- Session IV – Scientific and Engineering Applications -- A High Performance Computing System for Medical Imaging in the Remote Operating Room -- Parallel Partitioning Techniques for Logic Minimization Using Redundancy Identification -- Parallel and Distributed Frequent Itemset Mining on Dynamic Datasets -- A Volumetric FFT for BlueGene/L -- A Nearly Linear-Time General Algorithm for Genome-Wide Bi-allele Haplotype Phasing -- Keynote Address -- Energy Aware Algorithm Design via Probabilistic Computing: From Algorithms and Models to Moore’s Law and Novel (Semiconductor) Devices -- Session V – System Support in Overlay Networks, Clusters, and Grid -- Designing SANs to Support Low-Fanout Multicasts -- POMA: Prioritized Overlay Multicast in Ad Hoc Environments -- Supporting Mobile Multimedia Services with Intermittently Available Grid Resources -- Exploiting Non-blocking Remote Memory Access Communication in Scientific Benchmarks -- Session VI – Scheduling and Software Algorithms -- Scheduling Directed A-Cyclic Task Graphs on Heterogeneous Processors Using Task Duplication -- Double-Loop Feedback-Based Scheduling Approach for Distributed Real-Time Systems -- Combined Scheduling of Hard and Soft Real-Time Tasks in Multiprocessor Systems -- An Efficient Algorithm to Compute Delay Set in SPMD Programs -- Dynamic Load Balancing for I/O-Intensive Tasks on Heterogeneous Clusters -- Keynote Address -- Standards Based High Performance Computing -- Session VII – Network Design and Performance Issues -- Delay and Jitter Minimization in High Performance Internet Computing -- An Efficient Heuristic Search for Optimal Wavelength Requirement in Static WDM Optical Networks -- Slot Allocation Schemes for Delay Sensitive Traffic Support in Asynchronous Wireless Mesh Networks -- Multicriteria Network Design Using Distributed Evolutionary Algorithm -- Session VIII – Grid Applications and Architecture Support -- GridOS: Operating System Services for Grid Architectures -- Hierarchical and Declarative Security for Grid Applications -- A Middleware Substrate for Integrating Services on the Grid -- Performance Analysis of a Hybrid Overset Multi-block Application on Multiple Architectures -- Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors -- Keynote Address -- One Chip, One Server: How Do We Exploit Its Power? -- Session IX – Performance Evaluation and Analysis -- Data Locality Optimization for Synthesis of Efficient Out-of-Core Algorithms -- Performance Evaluation of Working Set Scheme for Location Management in PCS Networks -- Parallel Performance of the Interpolation Supplemented Lattice Boltzmann Method -- Crafting Data Structures: A Study of Reference Locality in ; Refinement-Based Pathfinding -- Improving Performance Analysis Using Resource Management Information -- Session X – Scheduling and Migration -- Optimizing Dynamic Dispatches through Type Invariant Region Analysis -- Thread Migration/Checkpointing for Type-Unsafe C Programs -- Web Page Characteristics-Based Scheduling -- Controlling Kernel Scheduling from User Space: An Approach to Enhancing Applications’ Reactivity to I/O Events -- High-Speed Migration by Anticipative Mobility.
• Sommario/riassunto: This book constitutes the refereed proceedings of the 10th International Conference on High-Performance Computing, HiPC 2003, held in Hyderabad, India in December 2003.The 48 revised full papers presented together with 5 keynote abstracts were carefully reviewed and selected from 164 submissions. The papers are organized in topical sections on performance issues and power-aware systems; distributed and network algorithms; routing in wireless, mobile, and cut-through networks; scientific and engineering applications; overlay networks, clusters, and grids; scheduling and software algorithms; network design and performance; grid applications and architecture support; performance analysis; scheduling and migration.