Bandwidth allocation for video under quality of service constraints / / Bushra Anjum, Harry Perros

• Record Nr.: UNINA9910132307603321
• Autore: Anjum Bushra
• Pubbl/distr/stampa: London, England ; ; Hoboken, New Jersey : , : ISTE : , : Wiley, , 2015; ©2015
• ISBN: 1-119-07317-0; 1-119-07315-4; 1-119-07316-2
• Descrizione fisica: 1 online resource (153 p.)
• Collana: FOCUS Networks and Telecommunication Series
• Disciplina: 005.746
• Soggetti: Data compression (Telecommunication)
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Description based upon print version of record.
• Nota di bibliografia: Includes bibliographical references and index.
• Nota di contenuto: Cover; Title Page; Copyright; Contents; Biographies; Bushra Anjum; Harry G. Perros; Acronyms; Introduction; I.1. QoS evolution in the IP network; I.1.1. Real Time Protocol (RTP); I.1.2. Integrated Services (IntServ); I.1.3. Differentiated Services (DiffServ); I.1.4. Multiprotocol Label Switching (MPLS); I.2. Elements of QoS architecture; I.2.1. Traffic classification; I.2.2. Queuing and scheduling policies; I.2.3. Policing of a packet flow; I.2.4. CAC; I.2.5. Traffic engineering; I.3. Problem definition: bandwidth allocation under QoS constraints; I.3.1. Bandwidth allocation based on the packet loss rate - literature reviewI.3.2. Bandwidth allocation based on end-to-end delay - literature review; I.4. Organization of the book; 1: Partitioning the End-to-End QoS Budget to Domains; 1.1. The need for adding percentiles; 1.2. Calculation of the weight function; 1.2.1. Exponential components with identical rate parameters; 1.2.2. Exponential components with different rate parameters; 1.2.3. Two-stage Coxian; 1.3. Interprovider quality of service; 1.4. Single source shortest path using Dijkstra's algorithm; 1.5. Conclusions; 2: Bandwidth Allocation for Video: MMPP2 Arrivals2.1. The queueing network under study; 2.2. Single-node decomposition; 2.3. Bandwidth estimation based on bounds; 2.4. Validation; 2.5. Conclusions; 3: Bandwidth Allocation for Video: MAP2 Arrivals; 3.1. The queueing ; network under study; 3.2. End-to-end delay estimation based on bounds; 3.2.1. The interpolation function; 3.3. Validation; 3.4. Video traces; 3.5. Conclusions; 4: Bandwidth Allocation for Video: Video Traces; 4.1. The proposed algorithm; 4.2. Test traces; 4.3. Bandwidth requirements for homogeneous flows; 4.4. Bandwidth allocation under percentile delay and jitter constraints4.5. Bandwidth allocation under percentile delay, average jitter and packet loss rate constraints; 4.6. Conclusions; Bibliography; Index
• Sommario/riassunto: We present queueing-based algorithms to calculate the bandwidth required for a video stream so that the three main Quality of Service constraints, i.e., end-to-end delay, jitter and packet loss, are ensured. Conversational and streaming video-based applications are becoming a major part of the everyday Internet usage. The quality of these applications (QoS), as experienced by the user, depends on three main metrics of the underlying network, namely, end-to-end delay, jitter and packet loss. These metrics are, in turn, directly related to the capacity of the links that the video traffic trave

Formal methods in computer-aided design : second international conference, FMCAD '98, Palo Alto, CA, USA, November 4-6, 1998 : proceedings / / Ganesh Gopalakrishnan, Phillip Windley (editors)

• Record Nr.: UNISA996465910703316
• Pubbl/distr/stampa: Berlin : , : Springer, , [1998]; ©1998
• ISBN: 3-540-49519-3
• Edizione: [1st ed. 1998.]
• Descrizione fisica: 1 online resource (X, 538 p.)
• Collana: Lecture notes in computer science ; ; 1522
• Disciplina: 621.392
• Soggetti: Digital integrated circuits - Computer-aided design; Computer engineering - Computer-aided design; Integrated circuits - Verification; Automatic theorem proving; Formal methods (Computer science)
• Lingua di pubblicazione: Inglese
• Formato: Materiale a stampa
• Livello bibliografico: Monografia
• Note generali: Bibliographic Level Mode of Issuance: Monograph
• Nota di bibliografia: Includes bibliographical references and index.
• Nota di contenuto: Minimalist Proof Assistants: Interactions of Technology and Methodology in Formal System Level Verification -- Reducing Manual Abstraction in Formal Verification of Out- of- Order Execution -- Bit-Level Abstraction in the Verification of Pipelined Microprocessors by Correspondence Checking -- Solving Bit-Vector Equations -- The Formal Design of 1M-Gate ASICs -- Design of Experiments for Evaluation of BDD Packages Using Controlled Circuit Mutations -- A Tutorial on Stålmarck’s Proof Procedure for Propositional Logic -- Almana: A BDD Minimization Tool Integrating Heuristic and RewritingMethods -- Bisimulation Minimization in an Automata-Theoretic Verification Framework -- Automatic Verification of Mixed-Level Logic Circuits -- A Timed Automaton-Based Method for Accurate Computation of Circuit Delay in the Presence of Cross-Talk -- Maximum Time Separation of Events in Cyclic Systems with Linear and Latest Timing Constraints -- Using MTBDDs for Composition and Model Checking of Real-Time Systems -- Formal Methods in CAD from an Industrial Perspective -- A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool -- Combined Formal Post- and Presynthesis Verification in High Level Synthesis -- Formalization and Proof of a Solution to the PCI 2.1 Bus Transaction Ordering Problem -- A Performance Study of BDD-Based Model Checking -- Symbolic Model Checking Visualization -- Input Elimination and Abstraction in Model Checking -- Symbolic Simulation of the JEM1 Microprocessor -- Symbolic Simulation: An ACL2 Approach -- Verification of Data-Insensitive Circuits: An In-Order-Retirement Case Study -- Combining Symbolic Model Checking with Uninterpreted Functions for Out-of-Order Processor Verification -- Formally Verifying Data and Control with Weak Reachability Invariants -- Generalized Reversible Rules -- An Assume-Guarantee Rule for Checking Simulation -- Three Approaches to Hardware Verification: HOL, MDG, and VIS Compared -- An Instruction Set Process Calculus -- Techniques for Implicit State Enumeration of EFSMs -- Model Checking on Product Structures -- BDDNOW: A Parallel BDD Package -- Model Checking VHDL with CV -- Alexandria: A Tool for Hierarchical Verification -- PV: An Explicit Enumeration Model-Checker.